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www.semtech.com page 1 sx1235 wireless & sensing datasheet rev 1 - december 2012 the sx1235 is a highly integrated rf transceiver optimized for operation compliant with etsi en 300 220 receiver category 1. in conjunction with an external saw filter the sx1235 is designed to pass the category 1 testing with substantial regulatory margin, simplifying end-user production test requirements. the sx1235 retains the highly integrated architecture of the sx123x family, minimizing external components while delivering the highest level of performance. for hybrid systems with non category 1 elements within an alarm system the sx1235 offers the advantage of programmable narrow-band and wide-band communication modes without the need tomodify external components. this makes the sx1235 suitable for integrated home automation, security and alarm systems that require legacy compatibility. ? category 1 social alarm systems ? category 1 fire, smoke and toxic gas detection ? category 1 lone worker systems ? home and building automation ? wireless alarm and security systems ? industrial monitoring and control ? optimised for the en 300-220-1 category 1 ? north america: fcc part 15 and japan: arib t-108 ? high sensitivity: down to -123 dbm at 1.2 kbps ? high selectivity: 60 db typ. acr ? high linearity: 50 db typ. of adjacent channel saturation ? 80 db blocking immunity, 100 db with saw ? image rejection of over 45 db ? low current: rx = 9.3 ma, 100na register retention ? programmable output power +20 dbm in 1 db steps ? optional high efficiency or fully regulated pa connections for reliable m2m performance and optimal battery lifetime ? voltage operation from 1.8 to 3.7 v ? narrowband integrated synthes izer with a resolution of 61 hz ? fsk, gfsk, msk, gm sk and ook modulation ? automated, fast frequency correction & timing recovery ? over 115 db dynamic range rssi ? packet engine with crc 64 byte fifo ? preamble and rssi based channel activity detection general description applications markets key product features ordering information part number package delivery moq / multiple SX1235IMLTRT qfn24 tape & reel 3000 pieces sx1235 transceiver en300 220 category 1 compliant transceiver
www.semtech.com page 2 section page table of contents sx1235 wireless & sensing datasheet rev 1 - december 2012 1. general description ........................................................................................................ ....................................... 10 1.1. simplified block diagram ................................................................................................. .............................. 10 1.2. pin and marking diagram ................................................................................................. .............................11 1.3. pin description ......................................................................................................... ......................................12 2. electrical characteristics ................................................................................................. ...................................... 13 2.1. esd notice ............................................................................................................... ..................................... 13 2.2. absolute maximum ratings ....................... .......................................................................... .......................... 13 2.3. operating range.......................................................................................................... .................................. 13 2.4. etsi category 1 specific ation ........................................................................................... ............................14 2.4.1. saw filter specification............................................................................................... ............................. 14 2.4.2. category 1 test conditions............................................................................................. .......................... 14 2.4.3. system performance (absolute units) with a saw as defined in 2.4.1.................................................... 14 2.4.4. system performa nce (regulatory margin) ................................................................................. ............... 15 2.4.5. measurement configuration for category 1 testing ...... ................................................................. .......... 15 2.4.6. 869 mhz category 1 reference design module sm1235 ...................................................................... .. 16 2.5. circuit specification .................................................................................................... ................................... 18 2.5.1. power consumption ...................................................................................................... ............................ 18 2.5.2. frequency synthesis.................................................................................................... ............................. 18 2.5.3. receiver ............................................................................................................... ..................................... 19 2.5.4. transmitter ............................................................................................................ .................................... 20 2.5.5. digital specification .................................................................................................. ................................. 21 3. chip description ........................................................................................................... ......................................... 22 3.1. power supply strategy .................................................................................................... .............................. 23 3.2. low battery detector ..................................................................................................... ................................ 23 3.3. frequency synthesis ..................................................................................................... ................................24 3.3.1. reference oscillator................................................................................................... ............................... 24 3.3.2. clkout output .......................................................................................................... .............................. 24 3.3.3. pll architecture....................................................................................................... ................................. 24 3.3.4. rc oscillator .......................................................................................................... ................................... 26 3.4. transmitter description ................................................................................................. .................................27 3.4.1. architecture description ............................................................................................... ............................. 27 3.4.2. bit rate setting ....................................................................................................... .................................. 27 3.4.3. fsk modulation......................................................................................................... ................................ 28 3.4.4. ook modulation......................................................................................................... ............................... 29 3.4.5. modulation shaping..................................................................................................... .............................. 29 3.4.6. rf power amplifiers.......................... .......................................................................... .............................. 29 3.4.7. high power +20 dbm operation .......................................................................................... .....................30 3.4.8. over current protection ............................................................................................... .............................31 3.5. receiver description .................................................................................................... ..................................32
www.semtech.com page 3 section page table of contents sx1235 wireless & sensing datasheet rev 1 - december 2012 3.5.1. overview ............................................................................................................... .................................... 32 3.5.2. automatic gain control - agc ........................................................................................... ....................... 32 3.5.3. rssi ................................................................................................................... ....................................... 33 3.5.4. channel filter ......................................................................................................... ................................... 34 3.5.5. fsk demodulator........................................................................................................ .............................. 35 3.5.6. ook demodulator........................................................................................................ ............................. 35 3.5.7. bit synchronizer ....................................................................................................... ................................. 37 3.5.8. frequency error indicator.............................................................................................. ............................ 37 3.5.9. afc ................................................................................................................... ........................................39 3.5.10. preamble detector ..................................................................................................... ............................. 39 3.5.11. image rejection mixer ................................................................................................ .............................40 3.5.12. image and rssi calibration............................................................................................ ........................ 40 3.6. temperature measurement .................................................................................................. ......................... 40 3.7. timeout function ......................................................................................................... .................................. 41 4. operating modes ............................................................................................................ ....................................... 42 4.1. general overview ......................................................................................................... ................................. 42 4.2. startup times............................................................................................................ ..................................... 42 4.2.1. transmitter startup time .................. ............................................................................ .............................43 4.2.2. receiver startup time.................................................................................................. ............................. 43 4.2.3. time to rssi evaluation ................................................................................................ ........................... 44 4.2.4. tx to rx turnaround time ............................................................................................... ......................... 44 4.2.5. rx to tx ............................................................................................................... ...................................... 44 4.2.6. receiver hopping, rx to rx ............................................................................................ ..........................45 4.2.7. tx to tx ............................................................................................................... ...................................... 45 4.3. receiver startup options ................................................................................................ ...............................46 4.4. receiver restarting methods.............................................................................................. ........................... 46 4.4.1. restart upon user request .............................................................................................. ........................ 46 4.4.2. automatic restart after valid packet rece ption ........................................................................ ................47 4.4.3. automatic restart when packet collision is detected.................................................................... ........... 47 4.5. top level sequencer ............................ ......................................................................... ................................48 4.5.1. sequencer states....................................................................................................... ............................... 48 4.5.2. sequencer transitions ................................................................................................. .............................49 4.5.3. timers ................................................................................................................. ...................................... 50 4.5.4. sequencer state machine ............................................................................................... ..........................51 5. data processing ............................................................................................................ ........................................ 52 5.1. overview ................................................................................................................. ....................................... 52 5.1.1. block diagram .......................................................................................................... ................................. 52 5.1.2. data operation modes ................................................................................................... ........................... 52 5.2. control block description................................................................................................ ............................... 53
www.semtech.com page 4 section page table of contents sx1235 wireless & sensing datasheet rev 1 - december 2012 5.2.1. spi interface.......................................................................................................... .................................... 53 5.2.2. fifo ................................................................................................................... ....................................... 54 5.2.3. sync word recognition.................................................................................................. ........................... 55 5.2.4. packet handler......................................................................................................... ................................. 56 5.2.5. control................................................................................................................ ....................................... 56 5.3. digital io pins mapping ................................................................................................. ................................57 5.4. continuous mode ......................................................................................................... ..................................58 5.4.1. general description.................................................................................................... ............................... 58 5.4.2. tx processing.......................................................................................................... .................................. 58 5.4.3. rx processing .......................................................................................................... ................................. 59 5.5. packet mode .............................................................................................................. .................................... 59 5.5.1. general description.................................................................................................... ............................... 59 5.5.2. packet format .......................................................................................................... ................................. 60 5.5.3. tx processing.......................................................................................................... .................................. 63 5.5.4. rx processing .......................................................................................................... ................................. 63 5.5.5. handling large packets ................................................................................................. ........................... 64 5.5.6. packet filtering....................................................................................................... ................................... 64 5.5.7. dc-free data mechanisms ............................................................................................... ........................66 5.5.8. beacon tx mode ......................................................................................................... .............................. 67 5.6. io-homecontrol? compatibility mode ............ ........................................................................... ...................... 67 6. description of the registers..................... .......................................................................... .................................... 68 6.1. register table summary ................................................................................................... ............................ 68 6.2. register map ............................................................................................................ ......................................71 7. application information .. .................................................................................................. ...................................... 85 7.1. crystal resonator specification.......................................................................................... ........................... 85 7.2. reset of the chip ........................................................................................................ ................................... 85 7.2.1. por.................................................................................................................... ....................................... 85 7.2.2. manual reset .......................................................................................................... ..................................86 7.3. reference designs ........................................................................................................ ................................ 86 7.4. top sequencer: listen mode examples ...... ............................................................................... ...................89 7.4.1. wake on preamble interrupt ................. ............................................................................ ........................ 89 7.4.2. wake on syncaddress in terrupt.......................................................................................... ...................... 91 7.5. top sequencer: beacon mode .............................................................................................. ........................94 7.5.1. timing diagram......................................................................................................... ................................. 94 7.5.2. sequencer configuration................................................................................................ ........................... 94 7.6. example crc calculation ................................................................................................. ............................96 7.7. example temperature reading ............................................................................................. ........................97 7.8. etsi category 1 quick start.................. ............................................................................ ............................ 98 7.8.1. pll settings ........................................................................................................... ................................... 98
www.semtech.com page 5 section page table of contents sx1235 wireless & sensing datasheet rev 1 - december 2012 7.8.2. channel filter settings ...................... .......................................................................... .............................. 98 7.8.3. image frequency ....................................................................................................... .............................100 7.8.4. tcxo settings .......................................................................................................... .............................. 100 8. packaging information ............................. ......................................................................... ................................... 101 8.1. package outline drawing .......................... ........................................................................ .......................... 101 8.2. recommended land pattern ................................................................................................. ...................... 101 8.3. thermal impedance ....................................................................................................... ..............................102 8.4. tape & reel specification................................................................................................ ............................ 102 9. revision history........................................................................................................... ........................................ 103
www.semtech.com page 6 sx1235 wireless & sensing datasheet rev 1 - december 2012 list of figures figure 1. block diagram ..................................................................................................... ......................................... 10 figure 2. pin diagram ....................................................................................................... ........................................... 11 figure 3. marking diagram ................................................................................................... ....................................... 11 figure 4. saw filter performance mask for guaranteed category 1 complia nce. ................................................. ... 14 figure 5. measurement configuratio n used for testing of the sx1235 reference de sign. ........................................ .... 15 figure 6. circuit schematic of the sx 1235 reference design used for regulatory testing. ..................................... ...... 16 figure 7. sx1235 reference design pc b layout, gives both +20 dbm rf output tx and category 1 rx. ............. 17 figure 8. simplified sx1235 block schematic diagram ......................................................................... ..................... 22 figure 9. tcxo connection ................................................................................................... ..................................... 24 figure 10. typical phase noise perf ormances of the low consumption and low phase noise plls. ..................... 25 figure 11. rf front-end architecture shows the internal pa configuration. .................................................. ........... 27 figure 12. receiver block diagram ........................................................................................... .................................. 32 figure 13. agc steps definition ............................................................................................. .................................... 33 figure 14. ook peak demodulato r description ................................................................................. ......................... 35 figure 15. floor threshold optimization ..................................................................................... ................................ 36 figure 16. bit synchronizer description ..................................................................................... ................................. 37 figure 17. fei process ...................................................................................................... .......................................... 38 figure 18. temperature sensor response ...................................................................................... ........................... 41 figure 19. startup process .................................................................................................. ........................................ 42 figure 20. time to rssi sample .............................................................................................. .................................... 44 figure 21. tx to rx turnaround .............................................................................................. .................................... 44 figure 22. rx to tx turnaround .............................................................................................. .................................... 44 figure 23. receiver hopping ................................................................................................. ...................................... 45 figure 24. transmitter hoppin g .............................................................................................. ..................................... 45 figure 25. timer1 and timer2 mechanism ...................................................................................... ............................ 50 figure 26. sequencer state machine .......................................................................................... ................................ 51 figure 27. sx1235 data processing conceptual vi ew ........................................................................... .................... 52 figure 28. spi timing diagram (single access) ............................................................................... ........................... 53 figure 29. fifo and shift register (sr) ..................................................................................... ................................ 54 figure 30. fifolevel irq source behavior .... ................................................................................ .............................. 55 figure 31. sync word recognition ............................................................................................ .................................. 56 figure 32. continuous mode conceptual view .................................................................................. ......................... 58 figure 33. tx processing in continuous mode ................................................................................. ........................... 58 figure 34. rx processing in continuous mode ................................................................................. .......................... 59 figure 35. packet mode conceptual view ...................................................................................... ............................. 60 figure 36. fixed length packet format ....................................................................................... ............................... 61 figure 37. variable length packet format .................................................................................... .............................. 62 figure 38. unlimited length packet format ................................................................................... ............................. 62 figure 39. manchester encoding /decoding ..................................................................................... ............................ 66 figure 40. data whitening polynomial ........................................................................................ ................................ 67 figure 41. por timing diagram ............................................................................................... .................................. 85
www.semtech.com page 7 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 42. manual reset timing diagram ........ .............................................................................. ............................. 86 figure 43. reference design - single rf input/outp ut, high efficiency pa .................................................... ........... 86 figure 44. reference design - with antenna switch up to +20dbm .............................................................. .............. 87 figure 45. reference design - with antenna switch and high efficiency pa .................................................... .......... 87 figure 46. reference design - single rf input/outp ut, high stability pa ..................................................... ............. 88 figure 47. listen mode: principle ............... ............................................................................ ..................................... 89 figure 48. listen mode with no preamble received ............................................................................ ....................... 89 figure 49. listen mode with pr eamble received ............................................................................... ......................... 90 figure 50. wake on preambledetect state machin e ............................................................................. ..................... 90 figure 51. listen mode with no syncaddress dete cted ......................................................................... ..................... 91 figure 52. listen mode with prea mble received and no syncaddress .. .......................................................... .......... 92 figure 53. listen mode with preamb le received & valid syncaddress ........................................................... ........... 92 figure 54. wake on syncaddress state machine ................................................................................ ...................... 93 figure 55. beacon mode timing diagram ....................................................................................... ............................ 94 figure 56. beacon mode state machine ........................................................................................ ............................. 94 figure 57. example crc code ................................................................................................. .................................. 96 figure 58. example temperature reading .......... ............................................................................ ............................ 97 figure 59. sx1235 optimised phase noise at 12.5 khz and 25 khz .............................................................. ............ 98 figure 60. sx1235 filter definitions and conven tions ........................................................................ ........................ 99 figure 61. sx1235 spurious imag e response frequency ......................................................................... .............. 100 figure 62. package outline drawing .......................................................................................... ............................... 101 figure 63. recommended land pattern ......................................................................................... .......................... 101 figure 64. tape & reel specification ........................................................................................ ................................ 102
www.semtech.com page 8 sx1235 wireless & sensing datasheet rev 1 - december 2012 list of tables table 1. sx1235 pinouts ...................................................................................................... ........................................ 12 table 2. absolute maximum ratings ................. ........................................................................... ................................ 13 table 3. operating range ..................................................................................................... ....................................... 13 table 4. absolute performance of the sx1235 reference design. ................................................................ .............. 14 table 5. sx1235 reference design regul atory margin to th e category 1 test limits. ............................................ ... 15 table 6. power consumption specification ....... .............................................................................. ............................. 18 table 7. frequency synthesizer specification ................................................................................. ............................. 18 table 8. receiver specification .............................................................................................. ...................................... 19 table 9. transmitter specification ........................................................................................... ..................................... 20 table 10. digital specification .............................................................................................. ........................................ 21 table 11. bit rate examples .................................................................................................. ...................................... 28 table 12. power amplifier mode se lection truth table ......................................................................... ...................... 29 table 13. high power settings ................................................................................................ ..................................... 30 table 14. absolute maximum rating, +20 dbm operation ......................................................................... ................. 30 table 15. operating range, +20dbm operation ...... ............................................................................ ........................ 30 table 16. trimming of the ocp current ........................................................................................ ............................... 31 table 17. lna gain control and performances .................................................................................. ......................... 32 table 18. rssismoothing options .............................................................................................. .................................. 34 table 19. available rxbw settings ............................................................................................ ................................... 34 table 20. preamble detector settings ......................................................................................... ................................. 39 table 21. rxtrigger settings to enable timeout interrupts .................................................................... ...................... 41 table 22. basic transceiver modes ............................................................................................ ................................. 42 table 23. receiver startup time summary ...................................................................................... ............................ 43 table 24. receiver startup options ........................................................................................... .................................. 46 table 25. sequencer states ................................................................................................... ...................................... 48 table 26. sequencer transition options ........... ............................................................................ ............................... 49 table 27. sequencer timer settings ........................................................................................... ................................. 50 table 28. status of fifo when switching between diffe rent modes of the chip .................................................. ....... 55 table 29. dio mapping, continuous mode ....................................................................................... ........................... 57 table 30. dio mapping, packet mode ........................................................................................... .............................. 57 table 31. crc description ................................................................................................... ....................................... 65 table 32. registers summary .................................................................................................. .................................... 68 table 33. register map ....................................................................................................... ......................................... 71 table 34. crystal specification .............................................................................................. ....................................... 85 table 35. listen mode with preambledetect condition settings ................................................................. ................. 90 table 36. listen mode with preambl edetect condition recommended dio mapping ................................................ 91 table 37. listen mode with sync address condition settings ........... ......................................................... .................. 93 table 38. listen mode with preambl edetect condition recommended dio mapping ................................................ 93 table 39. beacon mode settings ............................................................................................... .................................. 95 table 40. category 1 narrowband filt er settings for sx1235 ................................................................... ................... 99 table 41. sx1235 image and interm ediate frequency values. .................................................................... ............. 100
www.semtech.com page 9 sx1235 wireless & sensing datasheet rev 1 - december 2012 table 42. revision history ................................................................................................... ....................................... 103
www.semtech.com page 10 sx1235 wireless & sensing datasheet rev 1 - december 2012 this product datasheet contains a detailed description of the sx1235 performance and functi onality. please consult the semtech website for the la test updates or errata. 1. general description the sx1235 is a single-chip integrated transceiver circuit that is optimized for en 30 0 220-1 category 1 receiver applications. the fully integrated architecture of the transceiver is combined with an automated packet engine and top level sequencer. in conjunction with a 64 byte fifo these automate the entire proce ss of packet transmi ssion, reception and acknowledgement without incurring the consumption penalty co mmon to many transceivers th at feature an on-chip mcus. being easily configurable, it greatly si mplifies system design and reduces external mcu workload to a minimum. the small external bom is limited to a quartz crystal frequency reference, passive decoupling, matching and filtering components. sx1235 is intended for use as a high-performance, low-cos t, fsk and ook rf transceiver for robust, frequency agile, half-duplex, bidirectional rf links. where stable and constant rf performance is required over the full operating range of the device down to 1.8 v the receiver and pa are fully regulat ed. for transmit intensive applic ations - a high efficiency pa can be selected to optimize the current consumption. the sx1235 features high receiver sensitivity and low receiv e current, equating to a high link budget, 143db (-123dbm sensitivity in conjunction with +20dbm pout) and long ba ttery life. the sx1235 complies with both etsi and fcc regulatory requirements and is available in a 5 x 5 mm qfn 24 lead package. 1.1. simplified block diagram figure 1. block diagram
www.semtech.com page 11 sx1235 wireless & sensing datasheet rev 1 - december 2012 1.2. pin and marking diagram the following diagram shows the pin arrangement of the qfn package, top view. figure 2. pin diagram figure 3. marking diagram notes yyww indicates the date code xxxxxx.xxxxxx refers to the lot number
www.semtech.com page 12 sx1235 wireless & sensing datasheet rev 1 - december 2012 1.3. pin description table 1 sx1235 pinouts number name type description 0 ground - exposed ground pad 1 vbat1 - supply voltage 2vr_ana - regulated supply voltage for analogue circuitry 3 vr_dig - regulated supply voltage for digital blocks 4xta i/o xtal connection or tcxo input 5xtb i/o xtal connection 6 reset i/o reset trigger input 7dio0 i/o digital i/o, software configured 8 dio1/dclk i/o digital i/o, software configured 9dio2/data i/o digital i/o, software configured 10 dio3 i/o digital i/o, software configured 11 dio4 i/o digital i/o, software configured 12 dio5 i/o digital i/o, software configured 13 vbat2 - supply voltage 14 gnd - ground 15 sck i spi clock input 16 miso o spi data output 17 mosi i spi data input 18 nss i spi chip select input 19 rxtx o rx/tx switch control: high in tx 20 rfo o rf output 21 rfi i rf input 22 gnd o ground 23 pa_boost o optional high-power pa output 24 vr_pa o regulated supply for the pa
www.semtech.com page 13 sx1235 wireless & sensing datasheet rev 1 - december 2012 2. electrical characteristics 2.1. esd notice the sx1235 is a high performance r adio frequency device. it satisfies: ? class 2 of the jedec standard jesd22-a114-b (human body model) on all pins. ? class b of the jedec standard jesd22-a115-a (machine model) on all pins. ? class iv of the jedec standard jesd22-c101c (cha rged device model) on pins vr_ana, vr_dig, rfio, pa_boost, vr_pa, class iii on all other pins. esd precautions must be taken to avoid permanent damage. 2.2. absolute maximum ratings stresses above the values listed below may cause permanent device failure. exposure to absolute maximum ratings for extended periods may af fect device reliability. table 2 absolute maximum ratings 2.3. operating range table 3 operating range symbol description min max unit vddmr supply voltage -0.5 3.9 v tmr temperature -55 +115 c tj junction temperature - +125 c pmr rf input level - +10 dbm symbol description min max unit vddop supply voltage 1.8 3.7 v top operational temperature range -40 +85 c clop load capacitance on digital ports - 25 pf ml rf input level - +10 dbm
www.semtech.com page 14 sx1235 wireless & sensing datasheet rev 1 - december 2012 2.4. etsi catego ry 1 specification functionality that complies with the etsi en300 220 category 1 is only possible in conjunction with an external saw filter. to this end the specification of th e saw filter and the corresponding ov erall system performanc e is given here. 2.4.1. saw filter specification figure 4. saw filter performance mask for guaranteed category 1 compliance. 2.4.2. category 1 test conditions all receiver tests are performed with receiver bandwidth = 3.9 khz (single side bandwidth) as programmed in regrxbw, an afc ssbw of 7.81 khz (correspond s to a declared 18.7 khz dsbw -20 db ) receiving a 3 kbps pn15 sequence with 2 khz frequency deviation for a ber of 1% (bit synchronizer is enabled). the rf centre frequency is 869.21250 mhz. blocking tests are performed with an unmodulated interferer. t he wanted signal power for the blocking immunity and acr tests is set to -103.3 dbm (3 db above the calculated sensitiv ity limit of -106.3 dbm). saturati on testing in both the adjacent channel and higher offsets is performed at -63.3 dbm (43 db a bove the sensitivity limit of - 106.3 dbm). pll settings are as described in section 7.8.1. the reference circuit of section 2.4.6 is used with a saw filter for all measurements that respects the mask requirements of figure 4. category 1 performances are specified with a regulated 3.3 v supply and for operation at room temperature only. 2.4.3. system performance (absolute units) with a saw as defined in 2.4.1 table 4 absolute performance of the sx1235 reference design. symbol description conditions min typ max unit c1_rfs_f rf sensitivity fsk - -110 - dbm c1_acr adjacent channel rejection 25 khz -47 -44 - dbm c1_acs adjacent channel saturation 25 khz -16.3 -13.3 - dbm c1_bi blocking immunity 2 mhz 10 mhz -16.3 -14.3 -7.5 -7.5 - - dbm dbm
www.semtech.com page 15 sx1235 wireless & sensing datasheet rev 1 - december 2012 2.4.4. system performance (regulatory margin) table 5 sx1235 reference design regulatory margin to the category 1 test limits. 2.4.5. measurement configuration for category 1 testing figure 5. measurement configuration us ed for testing of the sx1235 reference design. c1_bs receiver saturation 2 mhz 10 mhz -14.3 -9.3 -7.5 -7.5 - - dbm dbm c1_img image rejection (bw= 3.9 khz or 7.81 khz) -500 khz -58.3 - - dbm symbol description conditions min typ max unit mc1_rfs_f margin to sensitivity limit - 3.7 - db mc1_acr margin to acr limit 25 khz 36 -db mc1_acs margin to acs limit 25 khz 36 -db mc1_bi margin to blocking limit 2 mhz 10 mhz 3 5 12.5 12.5 - - db db mc1_bs margin to saturation limit 2 mhz 10 mhz 5 10 12.5 12.5 - - db db mc1_img margin to image rejection limit (bs = 3.9 khz or 7.81 khz) -500 khz 10 - - db symbol description conditions min typ max unit
www.semtech.com page 16 sx1235 wireless & sensing datasheet rev 1 - december 2012 2.4.6. 869 mhz category 1 reference design module sm1235 figure 6. circuit schematic of the sx1235 reference design used for regulatory testing. 1 1 2 2 3 3 4 4 d d c c b b a a title number revision size a4 date: 12/7/2012 sheet of file: l:\pcblabo\ ..\e235v02b.schdoc drawn by: gnd 1nf c4 gnd gnd 15pf c3 100nf c6 100nf c1 100nf c2 gnd gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pod_in1 header 10x2 vcc_sx12xx gnd 3.3pf c14 5.6nh l3 nc c11 nc c13 5.6nh l4 8.2pf c8 gnd gnd 22pf c9 8.2pf c12 gnd 2.7nh l1 33nh l2 100nf c5 gnd vcc_sx12xx gnd gnd sx1235 class 1 reference design pcb_e235 v2b tco sck irq0 mosi irq1 nss clkout irq2 vdd gnd irq3 irq1 miso irq4 vcc rxtx nc reset nc nc nc nc 47pf c7 gnd tx matching and harmonic filtering 0r0 or nc r1 gnd nc c10 gnd j1 sma 1 2 sx1235 jumper 1 2 tcxo jumper vcc vcc_tcxo vcc vcc_sx12xx 2.7pf c15 2.7pf c16 18nh l5 18nh l6 gnd gnd rx saw filter circuit 40r f1 vcc_tcxo gnd gnd gnd gnd gnd gnd 1 gnd 2 out 3 vcc 4 u3 it3200c rfi 1 gnd 2 gnd 3 gnd 4 rfo 5 gnd 6 gnd 7 gnd 8 u2 tmx w341 g n d vbat1 1 vr_ana 2 vr_dig 3 xta 4 xtb 5 reset 6 nss 18 mosi 17 miso 16 sck 15 gnd 14 vbat2 13 dio0 7 dio1 8 dio2 9 dio3 10 dio4 11 dio5 12 vr_pa 24 pa_boost 23 gnd 22 rfi 21 rfo 20 rxtx 19 gnd 25 u1 sx1235 3.3pf c17 10nh l7 33pf c18 47pf c19 gnd j2 sma gnd gnd
www.semtech.com page 17 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 7. sx1235 reference design pcb layout, gives both +20 dbm rf output tx and category 1 rx.
www.semtech.com page 18 sx1235 wireless & sensing datasheet rev 1 - december 2012 2.5. circuit specification the tables below give the electrical spec ifications of the transceiver under the following conditions: supply voltage vbat1= vbat2 = vdd = 3.3 v, temperature = 25 c, f xosc = 32 mhz, f rf = 868 mhz, pout = +13 dbm, 2-level fsk modulation without pre-filtering, fda = 5 khz, bit rate = 4.8 kbps and terminated in a matched 50 ohm impedance, unless otherwise specified. note unless otherwise specified, the performance in the 915 mhz band is identical. 2.5.1. power consumption table 6 power consumption specification 2.5.2. frequency synthesis table 7 frequency synthesizer specification symbol description conditions min typ max unit iddsl supply current in sleep mode - 0.1 1 ua iddidle supply current in idle mode rc oscillator enabled - 1.2 - ua iddst supply current in standby mode crystal oscillator enabled - 1.3 1.5 ma iddfs supply current in synthesizer mode fsrx - 4.5 - ma iddr supply current in receive mode lnaboost = 00 - 9.3 - ma iddt supply current in transmit mode with impedance matching rfop = +20 dbm, on pa_boost rfop = +17 dbm, on pa_boost rfop = +13 dbm, on rfo pin rfop = + 7 dbm, on rfo pin - - - - 125 93 28 18 - - - - ma ma ma ma symbol description conditions min typ max unit fr synthesizer frequency range programmable 862 - 1020 mhz fxosc crystal oscillator frequency see section 7.1 -32 -mhz ts_osc crystal oscillator wake-up time with crystal specified in section 7.1 -250 - us ts_fs frequency synthesizer wake-up time to pll lock signal from standby mode - 60 - us ts_hop frequency synthesizer hop time at most 10 khz away from the target frequency 200 khz step 1 mhz step 5 mhz step 7 mhz step 12 mhz step 20 mhz step 25 mhz step - - - - - - - 20 20 50 50 50 50 50 - - - - - - - us us us us us us us fstep frequency synthesizer step fstep = fxosc/2 19 -61.0 - hz frc rc oscillator frequency after calibration - 62.5 - khz
www.semtech.com page 19 sx1235 wireless & sensing datasheet rev 1 - december 2012 note for maximum bit rate the maximum modulation index is 1. 2.5.3. receiver all receiver tests are performed with rxbw = 10 khz (single side bandwidth) as programmed in regrxbw , receiving a pn15 sequence. sensitivities are reported for a 0.1% ber ( with bit synchronizer enabled), unless otherwise specified. blocking tests are performed with an unmodulated interferer. the wanted signal power for the blocking immunity, acr, iip2, iip3 and amr tests is set 3 db above the receiver sensitivity level. table 8 receiver specification brf bit rate, fsk programma ble values (1) 1.2 - 300 kbps bro bit rate, ook programmable 1.2 - 32.768 kbps bra bit rate accuracy abs (wanted br - available br) - - 250 ppm fda frequency deviation, fsk (1) programmable fda + brf/2 =< 250 khz 0.6 - 200 khz symbol description conditions min typ max unit rfs_f direct tie of rfi and rfo pins, as shown in figure 43. fsk sensitivity, highest lna gain. fda = 5 khz, br = 1.2 kb/s fda = 5 khz, br = 4.8 kb/s fda = 40 khz, br = 38.4 kb/s* fda = 20 khz, br = 38.4 kb/s** fda = 62.5 khz, br = 250 kb/s*** - - - - - -119 -115 -105 -106 -92 - - - - - dbm dbm dbm dbm dbm split rf paths, as shown in figure 44, lnaboost is turned on, the rf switch insertion loss is not accounted for. fda = 5 khz, br = 1.2 kb/s fda = 5 khz, br = 4.8 kb/s fda = 40 khz, br = 38.4 kb/s* fda = 20 khz, br = 38.4 kb/s** fda = 62.5 khz, br = 250 kb/s*** - - - - - -123 -119 -110 -110 -97 - - - - - dbm dbm dbm dbm dbm rfs_o ook sensitivity, highest lna gain conditions of figure 43 br = 4.8 kb/s br = 32 kb/s - - -117 -108 - - dbm dbm ccr co-channel rejection - -8 - db acr adjacent channel rejection fda = 2 khz, br = 1.2kb/s, rxbw = 5.2khz offset = +/- 25 khz -54-db fda = 5 khz, br=4.8kb/s offset = +/- 25 khz offset = +/- 50 khz - - 50 50 - - db db bi blocking immunity offset = +/- 1 mhz offset = +/- 2 mhz offset = +/- 10 mhz - - - 73 78 87 - - - db db db amr am rejection, am modulated interferer with 100% modulation depth, fm = 1 khz, square offset = +/- 1 mhz offset = +/- 2 mhz offset = +/- 10 mhz - - - 73 78 87 - - - db db db
www.semtech.com page 20 sx1235 wireless & sensing datasheet rev 1 - december 2012 * rxbw = 83 khz (single side bandwidth) ** rxbw = 50 khz (single side bandwidth) *** rxbw = 250 khz (single side bandwidth) 2.5.4. transmitter table 9 transmitter specification iip2 2nd order input intercept point unwanted tones are 20 mhz above the lo highest lna gain -+57-dbm iip3 3rd order input intercept point unwanted tones are 1mhz and 1.995 mhz above the lo highest lna gain g1 lna gain g2, 4 db sensitivity hit - - -12 -8 - - dbm dbm bw_ssb single side channel filter bw programmable 2.7 - 250 khz imr image rejection wanted signal 3db over sens ber=0.1% -48-db ima image attenuation - 56 - db dr_rssi rssi dynamic range agc enabled min max - - -127 0 - - dbm dbm symbol description conditions min typ max unit rf_op rf output power in 50 ohms on rfo pin (high efficiency pa). programmable with steps max min +11 - +14 -1 - - dbm dbm rf_ op_v rf output power stability on rfo pin versus voltage supply. vdd = 2.5 v to 3.3 v vdd = 1.8 v to 3.7 v - - 3 8 - - db db rf_oph rf output power in 50 ohms, on pa_boost pin (regulated pa). programmable with 1 db steps max min - - +17 +2 - - dbm dbm rf_oph _max max rf output power, on pa_boost pin high power mode - +20 - dbm rf_ oph_v rf output power stability on pa_boost pin versus voltage supply. vdd = 2.4 v to 3.7 v - 1 - db rf_t rf output power stability versus temperature on both rf pins. from t = -40 c to +85 c - +/-1 - db phn transmitter phase noise low consumption pll, 915 mhz 50 khz offset 400 khz offset 1 mhz offset - - - -102 -114 -120 - - - dbc/ hz low phase noise pll, 915 mhz 50 khz offset 400 khz offset 1 mhz offset - - - -106 -117 -122 - - - dbc/ hz
www.semtech.com page 21 sx1235 wireless & sensing datasheet rev 1 - december 2012 2.5.5. digital specification conditions: temp = 25c, vdd = 3.3v, fxosc = 32 mhz, unless otherwise specified. table 10 digital specification acp transmitter adjacent channel power (measured at 25 khz off- set) bt=1. measurement conditions as defined by en 300 220-1 v2.4.1 ---37dbm ts_tr transmitter wake up time, to the first rising edge of dclk frequency synthesizer enabled, paramp = 10us, br = 4.8 kb/s - 120 - us symbol description conditions min typ max unit v ih digital input level high 0.8 - - vdd v il digital input level low - - 0.2 vdd v oh digital output level high imax = 1 ma 0.9 - - vdd v ol digital output level low imax = -1 ma - - 0.1 vdd f sck sck frequency - - 10 mhz t ch sck high time 50 - - ns t cl sck low time 50 - - ns t rise sck rise time - 5 - ns t fall sck fall time - 5 - ns t setup mosi setup time from mosi change to sck rising edge 30 - - ns t hold mosi hold time from sck rising edge to mosi change 20 - - ns t nsetup nss setup time from nss fa lling edge to sck rising edge 30 - - ns t nhold nss hold time from sck falling edge to nss rising edge, normal mode 100 - - ns t nhigh nss high time between spi accesses 20 - - ns t_data data hold and setup time 250 - - ns
www.semtech.com page 22 sx1235 wireless & sensing datasheet rev 1 - december 2012 3. chip description this section describes in depth the architecture of the sx12 35 low-power, highly integrated etsi category 1 compatible transceiver. the following figure shows a simplified block diagram of the sx1235. figure 8. simplified sx 1235 block schematic diagram sx1235 is a half-duplex, low-if transceiver. here the received rf signal is first amplified by the lna. the lna input is single ended to minimise the external bom and for ease of des ign. following the lna output the conversion to differential is made to improve the second order linearity and harmonic re jection. the signal is then down-converted to in-phase (i) and quadrature (q) components at the intermediate frequency (if) by the mixer stage. a pair of sigma delta adcs then perform data conversion, with all subsequent signal proce ssing and demodulation performed in the digital domain. the digital state machine also controls the automatic frequency co rrection (afc), received signal strength indicator (rssi) and automatic gain control (agc). it also features the higher-l evel packet and protocol level functionality of the top level sequencer. in the receiver operating mode two states of functionality are defined. upon initial transition to receiver operating mode the receiver is in the ?receiver-enabled? state. in this state the receiver awaits for either the user defined valid preamble or rs si detection criterion to be fulfilled. once met the receiver enters ?receiver-active? state. in this second state the received signal is processed by the packet engine and top level sequencer. the frequency synthes iser generates the local oscillato r (lo) frequency for both receiver and transmitter. the pll is optimized for user-transparent, low lock time, fast auto-ca librating operation. in transmission, frequency modulation is performed digitally within the pll bandwidth. sx1235 also feat ures optional pre-filtering of the bit stream to improve spectral purity.
www.semtech.com page 23 sx1235 wireless & sensing datasheet rev 1 - december 2012 sx1235 features a pair of rf power amplifiers. the first, con nected to rfo, can deliver up to +14 dbm, is unregulated for high power efficiency and can be connected directly to the rf receiver input via a pair of passive components to form a single antenna port high efficiency transceiver. the second pa, connected to the pa_boost pin and can deliver up to +20 dbm via a dedicated matching network. sx1235 also includes two timi ng references: an rc oscillator and a 32 mhz crystal oscillator. all major parameters of the rf front end and digital state machine are fully configurable via an spi interface which gives access to internal registers. this includes a mode auto sequ encer that oversees the transi tion and calibration of the sx1235 between intermediate modes of operation in the fastest time possible. 3.1. power supply strategy the sx1235 employs an advanced power supply scheme, whic h provides stable operating characteristics over the full temperature and voltage range of operation. this includes th e full output power of +17dbm which is maintained from 1.8 to 3.7 v. the sx1235 can be powered from any low-noise voltage source via pins vbat1 and vbat2. decoupling capacitors should be connected, as suggested in the reference design, on vr_p a, vr_dig and vr_ana pins to ensure a correct operation of the built-in voltage regulators. 3.2. low battery detector a low battery detector is also included allowing the ge neration of an interrupt signal in response to passing a programmable threshold adjust able through the register reglowbat . the interrupt signal can be mapped to any of the dio pins, by programming regdiomapping .
www.semtech.com page 24 sx1235 wireless & sensing datasheet rev 1 - december 2012 3.3. frequency synthesis 3.3.1. reference oscillator the crystal oscillator is the main timing reference of the sx1235 . it is used as a reference for the frequency synthesizer and as a clock for the digital processing. the xo startup time, ts_osc, depends on the actual xtal being connected on pins xta and xtb. the sx1232 optimizes the startup time and automatically triggers the pll when the xo signal is stable. an external clock can be used to replace the crystal o scillator, for instance a tight tolerance tcxo. to do so, tcxoinputon in regtcxo should be set to 1, and the external clock has to be provided on xta (pin 4). xtb (pin 5) should be left open. the peak-peak amplitude of the input signal must never exceed 1.8 v. please consult your tcxo supplier for an appropriate value of decoupling capacitor, c d . figure 9. tcxo connection 3.3.2. clkout output the reference frequency, or a fraction of it, can be provided on dio5 (pin 12) by modifying bits clkout in regdiomapping2 . two typical applications of the clkout output include: ? to provide a clock output for a companion processor, thus sa ving the cost of an addition al oscillator. clkout can be made available in any operation mode except sleep mode and is automatically enabled at power on reset. ? to provide an oscillator reference output . measurement of the clkout signal enab les simple software trimming of the initial crystal tolerance. note to minimize the current consumpti on of the sx1235, please ensure that t he clkout signal is disabled when not required. 3.3.3. pll architecture the local oscillator of the sx1235 is derived from a fractional-n pll that is referenced to the crysta l oscillator circuit. two plls are available for transmit mode operation - either low phase noise or low current consumption to maximize either transmit power consumption or transmit spectral purity. both plls feature a programmable bandwidth setting where one of four discrete preset bandwidths december be accessed. for reference the relative performance of both low consumption and low phase noise pll, for each programmable bandwidth setting, is shown in the following figure. xta xtb 32 mhz tcxo nc op vcc gnd c d vcc
www.semtech.com page 25 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 10. typical phase noise performances of the low consumption and low phase noise plls. note in receive mode, only the low consumption pll is available. the sx1235 pll embeds a 19-bit sigma-delta modulator and it s frequency resolution, constant over the whole frequency range, and is given by: f step f xosc 2 19 ---------------- =
www.semtech.com page 26 sx1235 wireless & sensing datasheet rev 1 - december 2012 the carrier frequency is programmed through regfrf , split across addresses 0x06 to 0x08: note the frf setting is split across 3 bytes. a change in the center frequenc y will only be taken into account when the least significant byte frflsb in regfrflsb is written. this allows for more complex modulation schemes such as m- ary fsk, where frequency modulation is achieved by changing the programmed rf frequency. 3.3.4. rc oscillator all timings in the low-power state of the top level sequencer rely on the accuracy of the internal low-power rc oscillator. this oscillator is automatically ca librated at the dev ice power-up, and it is a user-transpare nt process. for applications enduring large temperature variations, and fo r which the power supply is never removed, rc calibration can be performed upon user request. rccalstart in regosc triggers this calibration, and the flag rccaldone will be set automatically when the calibration is over. f rf f step frf 23 0 (,) =
www.semtech.com page 27 sx1235 wireless & sensing datasheet rev 1 - december 2012 3.4. transmitter description the transmitter of sx1235 comprises the frequency synthesize r, modulator and power amplifier blocks, together with the dc biasing and ramping functionality that is provided through the vr_pa block. 3.4.1. architecture description the architecture of the rf front end is shown in the following diagram. here we see that the unregulated pa0 is connected to the rfo pin features a single low power amplifier device. the pa_boost pin is connected to the internally regulated pa1 and pa2 circuits. here pa2 is a high power amplifier that permits continuous operation up to +17 dbm and duty cycled operation up to +20 dbm. for full details of operation at +20 dbm please consult section 3.4.7. figure 11. rf front-end architecture shows the internal pa configuration. 3.4.2. bit rate setting the bit rate setting is referenc ed to the crystal oscillator and provides a pr ecise means of setting the bit (or equivalently chip) rate of the radio. in continuous tr ansmit mode (section 5.1.2) the data stream to be transmitted can be input directly to the modulator via pin 9 (dio2/data) in an asynchronous manner, unless gaussian filtering is used, in which case the dclk signal on pin 10 (dio1/dclk) is used to synchronize the data stream. see section 3. 4.5 for details on the gaussian filter. in packet mode or in continuous mode with gaussian filt ering enabled, the bit rate (br) is controlled by bits bitrate in regbitratemsb and regbitratelsb note bitratefrac bits have no effect (i.e december be considered equal to 0) in ook modulation mode the quantity bitratefrac is hence designed to allow very high precision (max. 250 ppm calculation error) for any bitrate in the programmable range. table 11 below shows a range of standard bit rates and the accuracy to within which they december be reached. lna rec eiv er chain rfi local os c illator pa 0 pa 1 pa 2 pa _ b o os t rfo bitrate fxosc bitrate 15 0 (,) bitratefrac 16 ------------------------------- + ------------------------------------------------------------------------- =
www.semtech.com page 28 sx1235 wireless & sensing datasheet rev 1 - december 2012 table 11 bit rate examples 3.4.3. fsk modulation fsk modulation is performed inside the pll bandwidth, by chan ging the fractional divider ratio in the feedback loop of the pll. the large resolution of the sigma-delta modulator, a llows for very narrow freque ncy deviation. the frequency deviation f dev is given by: to ensure a proper modulation, the following limit applies: note no constraint applies to the modulation index of the tr ansmitter, but the frequency deviation must be set between 600 hz and 200 khz. type bitrate (15:8) bitrate (7:0) (g)fsk (g)msk ook actual br (b/s) classical modem baud rates (multiples of 1.2 kbps) 0x68 0x2b 1.2 kbps 1.2 kbps 1200.015 0x34 0x15 2.4 kbps 2.4 kbps 2400.060 0x1a 0x0b 4.8 kbps 4.8 kbps 4799.760 0x0d 0x05 9.6 kbps 9.6 kbps 9600.960 0x06 0x83 19.2 kbps 19.2 kbps 19196.16 0x03 0x41 38.4 kbps 38415.36 0x01 0xa1 76.8 kbps 76738.60 0x00 0xd0 153.6 kbps 153846.1 classical modem baud rates (multiples of 0.9 kbps) 0x02 0x2c 57.6 kbps 57553.95 0x01 0x16 115.2 kbps 115107.9 round bit rates (multiples of 12.5, 25 and 50 kbps) 0x0a 0x00 12.5 kbps 12.5 kbps 12500.00 0x05 0x00 25 kbps 25 kbps 25000.00 0x80 0x00 50 kbps 50000.00 0x01 0x40 100 kbps 100000.0 0x00 0xd5 150 kbps 150234.7 0x00 0xa0 200 kbps 200000.0 0x00 0x80 250 kbps 250000.0 0x00 0x6b 300 kbps 299065.4 watch xtal frequency 0x03 0xd1 32.768 kbps 32.768 kbps 32753.32 f dev f step fdev 13 0 (,) = f dev br 2 ------- 250 () khz +
www.semtech.com page 29 sx1235 wireless & sensing datasheet rev 1 - december 2012 3.4.4. ook modulation ook modulation is applied by switching on and off the powe r amplifier. digital control and smoothing are available to improve the transient power response of the ook transmitter. 3.4.5. modulation shaping modulation shaping can be applied in both ook and fsk modulation modes, to improve the narrowband response of the transmitter. both shaping features are controlled with paramp bits in regparamp . ? in fsk mode, a gaussian filter with bt = 0.5 or 1 is used to filter the modulation stream, at the input of the sigma-delta modulator. if the gaussian filter is en abled when the sx1232 is in continuous mode, dclk signal on pin 10 (dio1/ dclk) will trigger an in terrupt on the uc each time a new bit has to be transmitted. please re fer to section 5.4.2 for details. ? when ook modulation is used, the pa bias voltages are ra mped up and down smoothly when the pa is turned on and off, to reduce spectral splatter. note the transmitter must be restarted if the modulationshap ing setting is changed, in order to recalibrate the built-in filter. 3.4.6. rf power amplifiers three power amplifier blocks ar e embedded in the sx1235. the first one herein referred to as pa0, can generate high efficiency rf power into a 50 ohm load. the rf power is programmable between -1dbm and +14dbm. pa0 is connected to pin rfo (pin 22). pa1 and pa2 are both connected to pin pa_boost (pin 23). th ey can deliver up to +17 dbm in programmable step of 1db to the antenna, a specific impedance matching / harmonic filter ing design is required to ensure impedance transformation and regulatory compliance. the rf power is programmable between +2 dbm and +17 dbm. the high power mode allows to achieve fixed output power of +20 dbm. table 12 power amplifier mode selection truth table notes - for +20 dbm restrictions of operat ion, please consult the following section - to ensure correct operation at the highest power levels, please make sure to adjust the ocptrim accordingly in regocp. - if pa_boost pin is not used the pin can be left floating. paselect mode power range pout formula 0 pa0 output on pin rfo -1 to +14 dbm -1 dbm + outputpower 1 pa1 and pa2 combined on pin pa_boost +2 to +17 dbm +2 dbm + outputpower 1 pa1+pa2 on pa_boost with high output power +20dbm settings (see 3.4.7) +5 to +20 dbm +5 dbm + outputpower
www.semtech.com page 30 sx1235 wireless & sensing datasheet rev 1 - december 2012 3.4.7. high power +20 dbm operation the sx1235 has a high power +20 dbm capability on pa_boost pin, wit h the following settings: table 13 high power settings note - high power settings must be turned off when using pa0 - the over current protection limit should be adapted to the actual power level, in regocp specific absolute maximum ratings and op erating range restrictions apply to the +20dbm operation. they are listed in table 14 and table 15. table 14 absolute maximum rating, +20 dbm operation table 15 operating range, +20dbm operation the duty cycle of transmission at +20 dbm is limited to 1%, with a maximum vswr of 3:1 at antenna port, over the standard operating range [-40;+85 c]. for any other o perating condition, contact your semtech representative. register address value for high power default value pa0 or +17dbm description regpadac 0x5a 0x87 0x84 high power pa control symbol description min max unit dc_20dbm duty cycle of transmission at +20 dbm output - 1 % vswr_20dbm maximum vswr at antenna port, +20 dbm output - 3:1 - symbol description min max unit vddop_20dbm supply voltage, +20 dbm output 2.4 3.7 v
www.semtech.com page 31 sx1235 wireless & sensing datasheet rev 1 - december 2012 3.4.8. over current protection an over current protection block is built-in the chip. it helps preventing surge currents require d when the transmitter is used at its highest power levels, thus protecting the battery that december power the application. the current clamping value is controlled by ocptrim bits in regocp , and is calculated with the following formulas: table 16 trimming of the ocp current note imax sets a limit on the current drain of the power am plifier only, hence the maximum current drain of the sx1235 is equal to imax + i fs ocptrim i max imax formula 0 to 15 45 to 120 ma 45 + 5* ocptrim [ma] 16 to 27 130 to 240 ma -30 + 10* ocptrim [ma] 27+ 240 ma 240 ma
www.semtech.com page 32 sx1235 wireless & sensing datasheet rev 1 - december 2012 3.5. receiver description 3.5.1. overview the sx1235 features a digital receiver wit h the analog to digital conversion proc ess being performed di rectly following the lna-mixers block. the low-if receiver is able to handle ask, ook, (g)fsk a nd (g)msk modulation. all the filtering, demodulation, gain control, synchronization and packet hand ling is performed digitally, which allows a very wide range of bit rates and frequency deviations to be selected. the receiver is also capable of automatic gain calibration to improve precision on rssi measurement and enhanced image rejection. figure 12. receiver block diagram 3.5.2. automatic gain control - agc the agc feature allows receiver to hand le a wide rx input dynamic range from th e sensitivity level up to maximum input level of 0dbm or more, whilst optimizing the system linearity. table 17 hereafter shows typical nf and iip3 performances for the different lna gains. table 17 lna gain control and performances rx input level (pin) gain setting lnagain relative lna gain [db] nf [db] iip3 [dbm] pin <= agcthresh1 g1 ?001? 0 db 7 -12 agcthresh1 < pin <= agcthresh2 g2 ?010? -6 db 11 -8 agcthresh2 < pin <= agcthresh3 g3 ?011? -12 db 16 -5 agcthresh3 < pin <= agcthresh4 g4 ?100? -24 db 26 5 agcthresh4 < pin <= agcthresh5 g5 ?110? -26 db 34 10 agcthresh5 < pin g6 ?111? -48 db 44 10
www.semtech.com page 33 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 13. agc steps definition the global agc reference, reference all ag c thresholds, is determined as follows: ag c reference[dbm]=-174dbm+10*log(2* rxbw )+snr+ agcreferencelevel with snr = 8db, fixed value a detailed description of the receiver setup to enable the agc is provided in section 4.3. 3.5.3. rssi the rssi value reflects the incoming si gnal power provided at antenna port withi n the receiver bandwidth. the signal power is available in rssivalue . this value is absolute and its unit is in dbm with a resolution of 0.5db. the formula hereafter gives the relationship between the register value an d the absolute input signal level in dbm at antenna port: the rssi value can be compensated for to take into account the loss in the matching network or the gain of an additional lna, by using rssioffset . the offset can be chosen in 1db steps from -1 6 to +15db. when compensation is applied, the effective signal strengt h is read as follows: the rssi value is smoothed on a given number of measured rssi samples. the precision of the rssi value is related to the number of rssi samples used. rssismoothing selects the number of rssi samples from a minimum of 2 samples up to 256 samples in increments of power of 2. table 18 hereaf ter gives the estimation of the rssi accuracy for a 10db snr and the response time versus the number of rssi samples selected in rssismoothing . towards -125 dbm ? a g c r e f e r e n c e ? a g c t h r e s h 1 ? a g c t h r e s h 2 ? a g c t h r e s h 3 ? a g c t h r e s h 4 pin [dbm] ? a g c t h r e s h 5 agcstep1 agcstep2 agcstep3 agcstep4 agcstep5 g1 g2 g3 g4 g5 g6 higher sensitivity lower linearity lower noise figure lower sensitivity higher linearity higher noise figure [] [] db rssioffset dbm level rf rssivalue + ? = 2 [] 2 rssivalue dbm rssi ? =
www.semtech.com page 34 sx1235 wireless & sensing datasheet rev 1 - december 2012 table 18 rssismoothing options the rssi is calibrated, up the rfi pin, when image and rssi calibration is launched; please see section 3.5.12 for details. 3.5.4. channel filter the role of the channel filter is to filt er out the noise and interferers outside of the channel. channel filtering on the sx12 32 is implemented with a 16-tap finite impulse response (fir) filter, providing an outstandi ng adjacent chan nel rejection performance, even for narrowband applications. note to respect oversampling rules in the decimation chain of the receiver, the bit rate cannot be set at a higher value than 2 times the single-side receiv er bandwidth (bit rate < 2 x rxbw) the single-side channel filter bandwidth rxbw is controlled by the parameters rxbwmant and rxbwexp in regrxbw: the rx bandwidth mantissa ( rxbwmant ) also sets the intermediate freudians of the receiver. note that as a consequence, a different if december be used in afc and ensuing communication phases. the table below summarizes the available channel filter bandwidths and the corres ponding receiver in termediate frequency. (cryst al oscillator at 32 mhz): table 19 available rxbw settings rssismoothing number of samples estimated accuracy response time ?000? 2 6 db ?001? 4 5 db ?010? 8 4 db ?011? 16 3 db ?100? 32 2 db ?101? 64 1.5 db ?110? 128 1.2 db ?111? 256 1.1 db rxbwmant (binary/value) rxbwexp (decimal) rxbw (khz) intermediate frequency (khz) fsk / ook 10b / 24 7 2.6 166.66 01b / 20 7 3.1 200 00b / 16 7 3.9 250 10b / 24 6 5.2 166.66 01b / 20 6 6.3 200 00b / 16 6 7.8 250 10b / 24 5 10.4 166.66 01b / 20 5 12.5 200 00b / 16 5 15.6 250 10b / 24 4 20.8 166.66 01b / 20 4 25.0 200 00b / 16 4 31.3 250 10b / 24 3 41.7 166.66 () [] [] ms khz rxbw ing rssismooth ? + 4 2 1 rxbw fxosc rxbwmant 2 rxbwexp 2 + ----------------------------------------------------------------- - =
www.semtech.com page 35 sx1235 wireless & sensing datasheet rev 1 - december 2012 3.5.5. fsk demodulator the fsk demodulator of the sx1235 is designed to demodulate fsk, gfsk, msk and gmsk modulated signals. it is most efficient when the modulation index of the signal is greater than 0.5 and below 10: the output of the fsk demodulator can be fed to the bit synchronizer to provide the companion processor with a synchronous data stream in continuous mode. 3.5.6. ook demodulator the ook demodulator performs a comparison of the rssi outpu t and a threshold value. three different threshold modes are available, configured through bits ookthreshtype in regookpeak . the recommended mo de of operation is th e "peak" threshold mode, illustrated in figure 14: figure 14. ook peak demodulator description 01b / 20 3 50.0 200 00b / 16 3 62.5 250 10b / 24 2 83.3 166.66 01b / 20 2 100.0 200 00b / 16 2 125.0 250 10b / 24 1 166.7 166.66 01b / 20 1 200.0 200 00b / 16 1 250.0 250 other settings reserved n/a 0.5 2 f dev br ---------------------- 10 = zoom period as defined in ookpeakthreshdec decay in db as defined in ookpeakthreshstep fixed 6db difference rssi [dbm] noise floor of receiver ??floor?? threshold defined by ookfixedthresh time ??peak -6db?? threshold zoom
www.semtech.com page 36 sx1235 wireless & sensing datasheet rev 1 - december 2012 in peak threshold mode the comparison threshold level is the peak value of the rssi, reduced by 6db. in the absence of an input signal, or during the reception of a logical "0", the acquired peak value is decremented by one ookpeakthreshstep every ookpeakthreshdec period. when the rssi output is null for a long time (for instance after a long string of "0" received, or if no transmitter is present ), the peak threshold level will continue falling until it reaches the "f loor threshold", programmed in ookfixedthresh . the default settings of the ook demodulator lead to the perfor mance stated in the electrical specification. however, in applications in which sudden signal drops are awaited duri ng a reception, the three parameters should be optimized accordingly. 3.5.6.1. optimizing the floor threshold ookfixedthresh determines the sensitivity of the ook receiver, as it sets the comparison threshold for weak input signals (i.e. those close to the noise floor). significant sensitiv ity improvements can be gener ated if configured correctly. note that the noise floor of the receiver at the demodulator input depends on: ? the noise figure of the receiver. ? the gain of the receive chain from antenna to base band. ? the matching - including saw filter if any. ? the bandwidth of the channel filters. it is therefore important to note that the setting of ookfixedthresh will be application dependa nt. the following procedure is recommended to optimize ookfixedthresh . figure 15. floor threshold optimization the new floor threshold value found during this test should be used for ook reception wi th those receiver settings. set sx1232 in ook rx mode adjust bit rate, channel filter bw default ookfixedthresh setting no input signal continuous mode optimization complete glitch activity on data ? monitor dio2/data pin increment ookfixedthresh
www.semtech.com page 37 sx1235 wireless & sensing datasheet rev 1 - december 2012 3.5.6.2. optimizing ook demodu lator for fast fading signals a sudden drop in signal strength can cause the bit error rate to increase. for applications where the expected signal drop can be estimated, the following ook demodulator parameters ookpeakthreshstep and ookpeakthreshdec can be optimized as described below for a given number of threshold decrements per bit. refer to regookpeak to access those settings. 3.5.6.3. alternative ook demodulator threshold modes in addition to the peak ook threshold mode, the user can alternatively select two other types of threshold detectors: ? fixed threshold: the value is selected through ookfixedthresh ? average threshold: data supplied by the rssi block is av eraged, and this operation mode should only be used with dc-free encoded data. 3.5.7. bit synchronizer the bit synchronizer is a block that provi des a clean and synchronized digital output, free of glitches. its output is made available on pin dio1/dclk in continuous mode and can be di sabled through register settings. however, for optimum receiver performance its use when running continuous mode is strongly advised. the bit synchronizer is automatically activated in packet mode. its bit rate is controlled by bitratemsb and bitratelsb in regbitrate. figure 16. bit synchronizer description to ensure correct operation of the bit synchronizer , the following conditions have to be satisfied: ? a preamble (0x55 or 0xaa) of at least 12 bits is required for synchronization, the longer the synchronization the better the packet success rate ? the subsequent payload bit stream must have at least one tran sition form '0' to '1' or '1' to '0 every 16 bits during data transmission ? the bit rate matching between the transmitter and the receiver must be better than 6.5%. 3.5.8. frequency error indicator raw demodulator output (fsk or ook) dclk data bitsync output to pin data and dclk in continuous mode
www.semtech.com page 38 sx1235 wireless & sensing datasheet rev 1 - december 2012 this function provides information about the frequ ency error of the local oscillator (lo) compared with the carrier frequency of a modulated signal at the input of the receiver. when the fe i block is launched, the frequency error is measured and the signed result is loaded in feivalue in regfei , in 2?s complement format. the time required for an fei evaluation is 4 times the bit period. to ensure a proper behavior of the fei: ? the operation must be done during the reception of preamble ? the sum of the frequency offset and the 20 db signal b andwidth must be lower than the base band filter bandwidth the 20 db bandwidth of the signal can be evaluated as follows (double-side bandwidth): the frequency error, in hz, can be calculated with the following formula: figure 17. fei process bw 20 db 2 f dev br 2 ------- + ?? ?? = fei f step feivalue = sx1232 in rx mode preamble-modulated input signal signal level > sensitivity set feistart = 1 feidone = 1 no yes read feivalue
www.semtech.com page 39 sx1235 wireless & sensing datasheet rev 1 - december 2012 3.5.9. afc the afc is based on the fei block, and therefore the same input signal and receiver setting conditions apply. when the afc procedure is done, afcvalue is directly subtracted to the register that defines the frequency of operation of the chip, f rf . the afc is executed each time the receiver is enabled, if afcautoon = 1. when the afc is enabled ( afcautoon = 1), the user has the option to: ? clear the former afc correction value, if afcautoclearon = 1 ? start the afc evaluation from the previously corrected frequ ency. this december be useful in systems in which the lo keeps on drifting in the ?same direction?. ageing compensation is a good example. the sx1232 offers an alternate receiver bandwidth setting during the afc phase, to accommodate large lo drifts. if the user considers that the received signal december be out of the receiver bandwidth, a higher channel filter bandwidth can be programmed in regafcbw , at the expense of the re ceiver noise floor, which will impact upon sensitivity. the fei is valid only during preamble, and therefore the preambledetect flag can be used to validate the current fei result and add it to the afc register. the link between preambledetect interrupt and the afc is controlled by startdemodonpreamble in regrxconfig . a detailed description of the receiver setup to enable the afc is provided in section 4.3. 3.5.10. preamble detector the preamble detector indicates the reception of a carrier modulated with a 0101...sequence. it is insensitive to the frequency offset, as long as the receiver bandwidth is large enough. the size of detection can be programmed from 1 to 3 bytes with preambledetectorsize in regpreambledetect as defined in the next table. table 20 preamble detector settings for proper operation, preambledetecttol should be set to be set to 10 (0x0a), with a qualifying preamble size of 2 bytes. preambledetect interrupt (either in regirqflags1 or mapped to a specific dio) goes high every time a valid preamble is detected, assuming preambledetectoron =1. the preamble detector can also be used as a gate to ensure that afc and agc are performed on valid preamble. see section 4.3 for details. preambledetectorsize # of bytes 00 1 01 2 (recommended) 10 3 11 reserved
www.semtech.com page 40 sx1235 wireless & sensing datasheet rev 1 - december 2012 3.5.11. image rejection mixer the sx1235 embeds a state of the art image rejection mixer (irm). its default rejection, with no calibration, is 35db typ. the iq signals can be calibrated by an embedded source, pu shing the image rejection to ty pically 48db. this process is fully automated and self-contained. 3.5.12. image and rssi calibration calibration of the i and q signal is required to improve the rssi precision, as well as goo d image rejection performance. on the sx1232, iq calibration is seamless an d user-transparent. calibration is launched: ? automatically at power on reset or after a manual reset of the chip (refer to section 7.2). for applications where the temperature remains stable, or if the image rejection is not a major co ncern, this one-shot calibration will suffice ? automatically when a pre-defined temperature change is observed ? upon user request, by setting bit imagecalstart in regimagecal , when the device is in standby mode. a selectable temperature change, set with tempthreshold (5, 10, 15 or 20c), is detected and reported in tempchange , if the temperature monitoring is turned on with tempmonitoroff =0 . this interrupt flag can be used by the application to l aunch a new image calibration at a convenient time if autoimagecalon =0, or immediately when this temp erature variation is detected, if autoimagecalon =1. the calibration process takes approximately 10ms. 3.6. temperature measurement a stand alone temperature measurement block is used in orde r to measure the temperature in any mode except sleep and standby. it is enabled by defau lt, and can be stopped by setting tempmonitoroff to 1. the result of the measurement is stored in tempvalue in regtemp . due to process variations, the absolute accuracy of the result is +/- 10 c. a more precise re sult needs initial calibration to be done externally.
www.semtech.com page 41 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 18. temperature sensor response an example code for the conversion to be applied to tempvalue to obtain the reading in c is shown in section 7. 3.7. timeout function the sx1235 includes a timeout function, whic h allows it to automatica lly shut-down the receiver after a receive sequence and therefore save energy. ? timeout interrupt is generated timeoutrxrssi x 16 x tbit after switching to rx mode if the rssi flag does not raise within this time frame ( rssivalue > rssithreshold ) ? timeout interrupt is generated timeoutrxpreamble x 16 x tbit after switching to rx mode if the preambledetect flag does not raise within this time frame ? timeout interrupt is generated timeoutsignalsync x 16 x tbit after switching to rx mode if the syncaddress flag does not raise within this time frame this timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power mode. to become active, these timeouts must also be enabled by setting the correct rxtrigger parameters in regrxconfig: table 21 rxtrigger settings to enable timeout interrupts receiver triggering event rxtrigger (2:0) timeout on rssi timeout on preamble timeout on syncaddress none 000 off off active rssi interrupt 001 active off preambledetect 110 off active rssi interrupt & preambledetect 111 active active
www.semtech.com page 42 sx1235 wireless & sensing datasheet rev 1 - december 2012 4. operating modes 4.1. general overview the sx1235 has several working modes, manually programmed in regopmode . fully automated mode selection, packet transmission and reception is also possible using the top level sequencer described in section 4.5. table 22 basic transceiver modes when switching from a mode to another, the sub-blocks are woken up according to a pre-defined and optimized sequence. 4.2. startup times the startup time of the transmitter or the receiver is dependan t upon which mode the transceiver was in at the beginning. for a complete description, figure 19 below shows a comple te startup process, from the lower power mode ?sleep?. figure 19. startup process ts_osc is the startup time of the crystal oscillator, and mainly depends on the characteristics of the crystal itself. ts_fs is the startup time of the pll, and it in cludes a systematic calibration of the vco. typical values of ts_osc and ts_fs are given in section 2.3. mode selected mode symbol enabled blocks 000 sleep mode sleep none 001 standby mode stdby top regulator and crystal oscillator 010 frequency synthesiser to tx frequency fstx frequency synthesizer at tx frequency (frf) 011 transmit mode tx frequency synthesizer and transmitter 100 frequency synthesiser to rx frequency fsrx frequen cy synthesizer at frequency for reception (frf-if) 101 receive mode rx frequency synthesizer and receiver sleep mode transmit stdby mode fstx fsrx receive timeline 0 ts_osc ts_osc +ts_fs ts_osc +ts_fs +ts_tr ts_osc +ts_fs +ts_re current drain iddsl iddst iddfs iddr (rx) or iddt (tx)
www.semtech.com page 43 sx1235 wireless & sensing datasheet rev 1 - december 2012 4.2.1. transmitter startup time the transmitter startup time, ts_tr, is calculated as follows, in when f sk modulation is selected: , where paramp is the ramp-up time programmed in regparamp and tbit is the bit time. in ook mode, this equation can be simplified to the following: 4.2.2. receiver startup time the receiver startup time, ts_re, only depends upon the receiver bandwidth effective at the ti me of startup. when afc is enabled ( afcautoon =1), afcbw should be used instead of rxbw to extract the receiver startup time: table 23 receiver startup time summary ts_re or later after setting the devic e in receive mode, any incoming packet will be detected and demodulated by the transceiver. rxbw if afcautoon=0 rxbwafc if afcautoon=1 ts_re (+/-5%) 2.6 khz 2.33ms 3.1 khz 1.94ms 3.9 khz 1.56ms 5.2 khz 1.18ms 6.3 khz 984us 7.8 khz 791us 10.4 khz 601us 12.5 khz 504us 15.6 khz 407us 20.8 khz 313us 25.0 khz 264us 31.3 khz 215us 41.7 khz 169us 50.0 khz 144us 62.5 khz 119us 83.3 khz 97us 100.0 khz 84us 125.0 khz 71us 166.7 khz 85us 200.0 khz 74us 250.0 khz 63us tbit paramp s tr ts + + = 2 1 25 . 1 5 _ tbit s tr ts + =
www.semtech.com page 44 sx1235 wireless & sensing datasheet rev 1 - december 2012 4.2.3. time to rssi evaluation the first rssi sample will be available ts _rssi after the receiver is ready, in other words ts_re + ts_rssi after the receiver was req uested to turn on. figure 20. time to rssi sample ts_rssi depends on the receiver bandwidth, as well as the rssismoothing option that was selected. the formula used to calculate ts_rssi is prov ided in section 3.5.3. 4.2.4. tx to rx turnaround time figure 21. tx to rx turnaround note the spi instruction times are omitted, as they can gene rally be very small as compared to other timings (up to 10mhz spi clock) 4.2.5. rx to tx figure 22. rx to tx turnaround fsrx rx rssi irq rssi sample ready timeline 0ts_re ts_re +ts_rssi tx mode 1. set new frf (*) 2. set rx mode timeline 0ts_hop +ts_re (*) optional rx mode rx mode 1. set new frf (*) 2. set tx mode timeline 0ts_hop +ts_tr (*) optional tx mode
www.semtech.com page 45 sx1235 wireless & sensing datasheet rev 1 - december 2012 4.2.6. receiver hopping, rx to rx two methods are possible: figure 23. receiver hopping the second method is quicker, and should be used if a very quick rf sniffing mechanism is implemented. 4.2.7. tx to tx figure 24. transmitter hopping rx mode, channel a 1. set new frf 2. set restartrxwithplllock timeline 0ts_hop +ts_re rx mode, channel b first method rx mode, channel a 1. set fasthopon =1 2. set new frf (*) 3. wait for ts_hop timeline 0 ~ts_hop rx mode, channel b second method (*) regfrflsb must be written to trigger a frequency change 1. set new frf (*) 2. set fstx mode fstx timeline ~ paramp +ts_hop ~paramp +ts_hop +ts_tr 0 tx mode, channel a tx mode, channel b set tx mode
www.semtech.com page 46 sx1235 wireless & sensing datasheet rev 1 - december 2012 4.3. receiver startup options the sx1235 receiver can automatically control the gain of its receiver chain (agc) and adjust its receiver lo frequency (afc). those processes are carried out on a packet-by-packet basis, and they occur: ? when the receiver is turned on ? when the receiver is restarted upon user request, through the use of trigger bits restartrxwithoutplllock or restartrxwithplllock , in regrxconfig. ? when the receiver is automat ically restarted after the re ception of a valid packet, or after a packet collision. automatic restart capabilities are detailed in section 4.4. several receiver startup options are offered in the state machine of the sx1235, and they are described in table 24: table 24 receiver startup options when agcautoon =0, the lna gain is manually selected by choosing lnagain bits in reglna. 4.4. receiver restarting methods it december be useful to restart the receiver, for example to prepare for the reception of a new signal whose strength december widely differ from the previous packet receiver, or whose carrier frequency december be different, required a new afc. a few options are proposed: 4.4.1. restart upon user request at any point in time, when the device is in receive mode, the user can restart the receiver; this is particularly useful in conjunction with the use of a timeout, whereby the receiver would need restarting if it had not detected any incoming packet after a few milliseconds of chan nel scanning. two options are available: ? no change in the local oscillator upon restart: the afc is disabled, and the frf register has not been changed through spi before the restart instruction: set bit restartrxwithoutplllock in regrxconfig to 1. ? local oscillator change upon restart: if afc is enabled ( afcautoon =1), and/or the frf register had been changed during the last rx period: set bit restartrxwithplllock in regrxconfig to 1. note modeready must be at logic level 1 for a new restartrx command to be taken into account triggering event realized function agcautoon afcautoon rxtrigger (2:0) none none 0 0 000 rssi interrupt agc 1 0 001 agc & afc 1 1 001 preambledetect agc 1 0 110 agc & afc 1 1 110 rssi interrupt & preambledetect agc 1 0 111 agc & afc 1 1 111
www.semtech.com page 47 sx1235 wireless & sensing datasheet rev 1 - december 2012 4.4.2. automatic restart after valid packet reception the bits autorestartrxmode in regsyncconfig control the automatic restart feature of the sx1235 receiver, when a valid packet has been received: ? if autorestartrxmode = 00 , the function is off, and the user should ma nually restart the receiver upon valid packet reception (see section 4.4.1 ). ? if autorestartrxmode = 01 , after the user has empt ied the fifo following a payloadready interrupt, the receiver will automatically restart itself after a delay of interpacketrxdelay , allowing for the distant transmitter to ramp down, hence avoiding a false rssi detection on the ?tail? of the previous packet. ? if autorestartrxmode = 10 should be used if the next reception is expected on a new frequency, i.e. frf is changed after the reception of the previous packet. an additional delay is systematically added, in order for the pll to lock at a new frequency. 4.4.3. automatic restart when packet collision is detected at any stage during reception, the receiv er is able to spontaneously detect a packet collision, and restart itself. collisions are detected by a sudden rise in received signal strength, de tected by the rssi blocks. this function can be useful in star network configurations, where a master node december be tr ansmitted packet at random times, from different end-points located at various distances. the collision detector is enabled by setting bit restartrxoncollision to 1. the decision to restart the receiver is based on the detection of rssi change. the sensitivity of the system can be adjusted in 1db steps, with rssicollisionthreshold in regrxconfig .
www.semtech.com page 48 sx1235 wireless & sensing datasheet rev 1 - december 2012 4.5. top level sequencer depending on the application, it is desirable to be able to change the mode of the circuit according to a predefined sequence without access to the serial inte rface. in order to define different seque nces or scenarios, a user-programmable state machine, called top level sequencer (sequencer in short), can automatically control the chip modes. the sequencer is activated by setting the sequencerstart bit in regseqconfig1 to 1 in sleep or standby mode (called initial mode). it is also possible to force the sequencer off by setting the stop bit in regseqconfig1 to 1 at any time. note sequencerstart and stop bit must never be set at the same time. 4.5.1. sequencer states the sequencer takes control of the chip operation over 4 possible states and 3 transitory states: table 25 sequencer states sequencer state description sequenceroff state the sequencer is not activated. sending a sequencerstart command will launch it. when coming from lowpowerselection state, the sequencer will be off, whilst the chip will return to its initial mode (either sleep or standby mode). idle state the chip is in low- power mode, either standby or sleep , as defined by idlemode in regseqconfig1 . the sequencer waits only for the t1 interrupt. transmit state the transmitter in on. receive state the receiver in on. packetreceived the receiver is on and a packet has been received. it is stored in the fifo. lowpowerselection selects low power state ( sequenceroff or idle state) rxtimeout defines the action to be taken on a rxtimeout interrupt. rxtimeout interrupt can be a timeoutrxrssi , timeoutrxpreamble or timeoutsignalsync interrupt.
www.semtech.com page 49 sx1235 wireless & sensing datasheet rev 1 - december 2012 4.5.2. sequencer transitions the transitions between sequencer states are listed in the forthcoming table. table 26 sequencer transition options variable transition idlemode selects the chip mode during idle state: 0: standby mode 1: sleep mode fromstart controls the sequencer transition when the sequencerstart bit is set to 1 in sleep or standby mode: 00: to lowpowerselection 01: to receive state 10: to transmit state 11: to transmit state on a fifothreshold interrupt lowpowerselection selects sequencer lowpower state after a to lowpowerselection transition 0: sequenceroff state with chip on initial mode 1: idle state with chip on standby or sleep mode depending on idlemode note: initial mode is the chip lowpower mode at sequencer start. fromidle controls the sequencer transition from the idle state on a t1 interrupt: 0: to transmit state 1: to receive state fromtransmit controls the sequencer transition from the transmit state: 0: to lowpowerselection on a packetsent interrupt 1: to receive state on a packetsent interrupt fromreceive controls the sequencer transition from the receive state: 000 and 111: unused 001: to packetreceived state on a payloadready interrupt 010: to lowpowerselection on a payloadready interrupt 011: to packetreceived state on a crcok interrupt. if crc is wrong (corrupted packet, with crc on but crcautoclearon is off), the payloadready inte rrupt will drive the sequen cer to rxtimeout state. 100: to sequenceroff state on a rssi interrupt 101: to sequenceroff state on a syncaddress interrupt 110: to sequenceroff state on a preambledetect interrupt irrespective of this setting, transition to lowpowerselection on a t2 interrupt fromrxtimeout controls the state-mach ine transition from the receive state on a rxtimeout interrupt (and on payloadready if fromreceive = 011): 00: to receive state via receiverestart 01: to transmit state 10: to lowpowerselection 11: to sequenceroff state note: rxtimeout interrupt is a timeoutrxrssi , timeoutrxpreamble or timeoutsignalsync interrupt. frompacketreceived controls the state-machine transition from the packetreceived state: 000: to sequenceroff state 001: to transmit on a fifoempty interrupt 010: to lowpowerselection 011: to receive via fs mode, if frequency was changed 100: to receive state (no frequency change)
www.semtech.com page 50 sx1235 wireless & sensing datasheet rev 1 - december 2012 4.5.3. timers two timers (timer1 and timer2) are also available in order to define periodic sequences. these timers are used to generate interrupts, which can trigger transitions of the sequencer. t1 interrupt is generated (timer1resolution * timer1coefficient) after t2 interrupt or sequencerstart . command. t2 interrupt is generated (timer2resolution * timer2coefficient) after t1 interrupt . the timers? mechanism is summarized on the following diagram. figure 25. timer1 and timer2 mechanism note the timer sequence is completed independently of the actual sequencer state. thus, both timers need to be on to achieve a periodic cycling. table 27 sequencer timer settings variable description timer1resolution resolution of timer1 00: disabled 01: 64 us 10: 4.1 ms 11: 262 ms timer2resolution resolution of timer2 00: disabled 01: 64 us 10: 4.1 ms 11: 262 ms timer1coefficient multiplying coefficient for timer1 timer2coefficient multiplying coefficient for timer2 t2 interrupt t1 interrupt timer1 timer2 sequencer start
www.semtech.com page 51 sx1235 wireless & sensing datasheet rev 1 - december 2012 4.5.4. sequencer state machine the following graphs summarize every possible transition be tween each sequencer state. the sequencer states are highlighted in grey. the transitions are represented by arrows. the condition activating them is described over the transition arrow. for better readability, the start transitions are separated fr om the rest of the graph. transitory states are highlighted in light grey, and exit states are represented in red. it is also possible to force the sequencer off by setting the stop bit in regseqconfig1 to 1 at any time. figure 26. sequencer state machine use cases of the top sequencer are detailed in section 7. sequencer: start transitions sequencer: state machine transmit lowpower selection idle receive packet received rxtimeout if lowpowerselection = 1 on t1 if fromidle = 0 on packetsent if fromtransmit = 1 on payloadready if fromreceive = 001 on crcok if fromreceive = 011 on payloadready if fromreceive = 010 if fromrxtimeout = 01 if fromrxtimeout = 10 if frompacketreceived = 010 if frompacketreceived = 100 via fs mode if frompacketreceived = 011 on packetsent if fromtransmit = 0 via receiverestart if fromrxtimeout = 00 on rxtimeout on t2 on t1 if fromidle = 1 if lowpowerselection = 0 ( mode te initial mode ) on rssi if fromreceive = 100 on syncadress if fromreceive = 101 on preamble if fromreceive = 110 if fromrxtimeout = 11 if frompacketreceived = 000 sequencer off standby if idlemode = 0 sleep if idlemode = 1 transmit lowpower selection receive start if fromstart = 00 if fromstart = 01 if fromstart = 10 sequencer off sequencer off & initial mode = sleep or standby on sequencerstart bit rising edge on fifothreshold if fromstart = 11 on payloadready if fromreceive = 011 (crc failed and crcautoclearon =0)
www.semtech.com page 52 sx1235 wireless & sensing datasheet rev 1 - december 2012 5. data processing 5.1. overview 5.1.1. block diagram figure below illustrates the sx123 5 data processing circuit. its role is to interface the data to/from the modulator/ demodulator and the uc access points (spi and dio pins ). it also controls all the configuration registers. the circuit contains several control blocks wh ich are described in the following paragraphs. figure 27. sx1235 data processing conceptual view the sx1235 implements several data operation modes, each with their own data path through the data processing section. depending on the data operation mode selected, some cont rol blocks are active whilst others remain disabled. 5.1.2. data operation modes the sx1235 has two different data operation modes selectable by the user: ? continuous mode: each bit transmitted or received is accessed in re al time at the dio2/data pin. this mode december be used if adequate external signal processing is available. ? packet mode (recommended): user only provides/retrieves payload bytes to/from the fifo. the packet is automatically built with preamble, sync word, and optional crc and dc-f ree encoding schemes the reverse operation is performed in reception. the uc processing overhead is hence signific antly reduced compared to continuous mode. depending on the optional features activated (crc, etc) the maximum payload length is limited to 255, 2047 bytes or unlimited. each of these data operation modes is fully described in the following sections. control spi packet handler sync recog. dio1 miso mosi sck nss rx tx tx/rx data fifo (+sr) potential datapaths (data operation mode dependant) dio2 dio0 dio3 dio4 dio5
www.semtech.com page 53 sx1235 wireless & sensing datasheet rev 1 - december 2012 5.2. control block description 5.2.1. spi interface the spi interface gives access to the configuration register via a synchronous full-duplex pr otocol corresponding to cpol = 0 and cpha = 0 in motorola/freescale nome nclature. only the slave side is implemented. three access modes to the registers are provided: ? single access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access. the nss pin goes low at the begin of the frame and goes high after the data byte. ? burst access: the address byte is followed by several data bytes. the address is automati cally incremented internally between each data byte. this mode is available for both read and write accesses. the nss pin goes low at the beginning of the frame and stay low between each byte . it goes high only afte r the last byte transfer. ? fifo access: if the address byte corr esponds to the address of the fifo, then succeeding data byte will address the fifo. the address is not automatically incremented but is me morized and does not need to be sent between each data byte. the nss pin goes low at the beginning of the frame and stay low between each byte. it goes high only after the last byte transfer. figure below shows a typical spi single access to a register. figure 28. spi timing diagram (single access) mosi is generated by th e master on the falling edge of sck and is sample d by the slave (i.e. this spi interface) on the rising edge of sck. miso is generated by the slav e on the falling edge of sck. a transfer always starts by the nss pin going lo w. miso is high impedance when nss is high. the first byte is the address byte. it is made of: ? wnr bit, which is 1 for write access and 0 for read access ? 7 bits of address, msb first the second byte is a data byte, either se nt on mosi by the master in case of a write access, or received by the master on miso in case of read access. the data byte is transmitted msb first. proceeding bytes december be sent on mosi (for write access) or received on miso (for read access) without rising nss and re-sending the address. in fifo mode, if the address was the fifo address then the bytes will be written / read at the fifo address. in burst mode, if the address was not the fifo address, then it is automatic ally incremented at each new byte received.
www.semtech.com page 54 sx1235 wireless & sensing datasheet rev 1 - december 2012 the frame ends when nss goes high. the next frame must start with an address byte. the single access mode is actually a special case of fifo / burst mode with only 1 data byte transferred. during the write access, the byte transferred from the slave to the master on the miso line is the value of the written register before the write operation. 5.2.2. fifo 5.2.2.1. overview and shift register (sr) in packet mode of operation, both data to be transmitted and that has been received are stored in a configurable fifo (first in first out) device. it is acce ssed via the spi interface and provides several interrupts for transfer management. the fifo is 1 byte wide hence it only performs byte (paralle l) operations, whereas the demodulator functions serially. a shift register is therefore employed to interface the two device s. in transmit mode it takes bytes from the fifo and outputs them serially (msb first) at the programmed bit rate to the modu lator. similarly, in rx the sh ift register gets bit by bit data from the demodulator and writes th em byte by byte to the fifo. th is is illustrated in figure below. figure 29. fifo and shift register (sr) note when switching to sleep mode, the fifo can only be used once the modeready flag is set (quasi immediate from all modes except from tx) 5.2.2.2. size the fifo size is fixed to 64 bytes. 5.2.2.3. interrupt sources and flags ? fifoempty : fifoempty interrupt source is high when byte 0, i.e. whole fi fo, is empty. otherwise it is low. note that when retrieving data from the fifo, fifoempty is updated on nss fa lling edge, i.e. when fifoempty is updated to low state the currently started read operation mu st be completed. in other words, fifoempty state must be checked after each read operation for a decision on the next one ( fifoempty = 0: more byte(s) to read; fifoempty = 1: no more byte to read). ? fifofull : fifofull interrupt source is high when the last fifo byte , i.e. the whole fifo, is full. otherwise it is low. ? fifooverrunflag : fifooverrunflag is set when a new byte is written by the user (in tx or standby modes) or the sr (in rx mode) while the fifo is already full. da ta is lost and the flag sh ould be cleared by writing a 1, note that the fifo will also be cleared. ? packetsent : packetsent interrupt source goes high when the sr's last bit has been sent. ? fifolevel : threshold can be programmed by fifothreshold in regfifothresh . its behavior is illust rated in figure below. data tx/rx 8 1 sr (8bits) byte0 byte1 fifo msb lsb
www.semtech.com page 55 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 30. fifolevel irq source behavior note - fifolevel interrupt is updated only after a read or write operation on the fifo. thus the interrupt cannot be dynamically updated by only changing the fifothreshold parameter - fifolevel interrupt is valid as long as fifofull does not occur. an empty fifo will restor e its normal operation 5.2.2.4. fifo clearing table below summarizes the status of the fi fo when switching between different modes table 28 status of fifo when switching between different modes of the chip 5.2.3. sync word recognition 5.2.3.1. overview sync word recognition (als o called pattern recognition) is activated by setting syncon in regsyncconfig . the bit synchronizer must also be activated in conti nuous mode (automatically done in packet mode). the block behaves like a shift register; it continuously co mpares the incoming data with its internally programmed sync word and sets syncaddressmatch when a match is detected. this is illustrated in figure 31 below. from to fifo status comments stdby sleep not cleared sleep stdby not cleared stdby/sleep tx not cleared to allow the user to write the fifo in stdby/sleep before tx stdby/sleep rx cleared rx tx cleared rx stdby/sleep not cleared to allow the user to read fifo in stdby/sleep mode after rx tx any cleared # of bytes in fifo fifolevel 0 1 b b+1
www.semtech.com page 56 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 31. sync word recognition during the comparison of the demodulated data, the fi rst bit received is compared with bit 7 (msb) of regsyncvalue1 and the last bit received is compared with bit 0 (lsb) of the la st byte whose address is determ ined by the length of the sync word. when the programmed sync word is detected the user can assu me that this incoming packet is for the node and can be processed accordingly. syncaddressmatch is cleared when leaving rx or fifo is emptied. 5.2.3.2. configuration ? size: sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via syncsize in regsyncconfig . in packet mode this field is also used for sync word generation in tx mode. ? value: the sync word va lue is configured in syncvalue(63:0) . in packet mode this field is also used for sync word generation in tx mode. note syncvalue choices containing 0x00 bytes are not allowed 5.2.4. packet handler the packet handler is the block used in packet mode. its functionality is fully described in section 5.5. 5.2.5. control the control block configures and controls the full chip's beha vior according to the settings programmed in the configuration registers. rx data (nrz) dclk bit n-x = sync_value[x] bit n-1 = sync_value[1] bit n = sync_value[0] syncaddressmatch
www.semtech.com page 57 sx1235 wireless & sensing datasheet rev 1 - december 2012 5.3. digital io pins mapping six general purpose io pins are available on the sx1235, and their configuration in continuous or packet mode is controlled through regdiomapping1 and regdiomapping2. table 29 dio mapping, continuous mode table 30 dio mapping, packet mode diox mapping sleep standby fsrx/tx rx tx 00 syncaddress txready 01 rssi / preambledetect - 10 rxready txready 11 00 01 rssi / preambledetect - 10 11 00 01 10 11 00 timeout - 01 rssi / preambledetect - 10 11 - 00 01 10 timeout - 11 - 00 clkout if rc 01 10 rssi / preambledetect - 11 - plllock modeready modeready dio0 dio1 dio3 dio2 - - - dio5 dio4 - - - - - - - - - - - - modeready modeready dclk data data data clkout clkout tempchange / lowbat tempchange / lowbat tempchange / lowbat plllock data - - - - - diox mapping sleep standby fsrx/tx rx tx 00 payloadready packetsent 01 crcok - 10 11 - 00 fifolevel 01 fifoempty 10 fifofull 11 00 fifofull 01 rxready - 10 timeout fifofull 11 syncaddress fifofull 00 fifoempty 01 txready 10 fifoempty 11 fifoempt y 00 - 01 10 timeout - 11 rssi / preambledetect - 00 clkout if rc 01 10 11 - fifoempty modeready fifoempty fifoempty fifoempty dio5 - plllock -data clkout clkout modeready dio4 - plllock - - tempchange / lowbat tempchange / lowbat dio3 - fifoempty dio2 - fifofull fifofull fifofull fifofull fifoempty dio1 - fifolevel fifoempty fifoempty fifolevel fifofull fifofull dio0 - - - tempchange / lowbat tempchange / lowbat
www.semtech.com page 58 sx1235 wireless & sensing datasheet rev 1 - december 2012 5.4. continuous mode 5.4.1. general description as illustrated in figure 32, in continuous mode the nrz data to (from) the (de)modulator is direct ly accessed by the uc on the bidirectional dio2/data pin. the fifo and packet handler are thus inactive. figure 32. continuous mode conceptual view 5.4.2. tx processing in tx mode, a synchronous data clock for an external uc is provided on dio1/dclk pin. clo ck timing with respect to the data is illustrated in figure 33. data is internally sampled on the ri sing edge of dclk so th e uc can change logic state anytime outside the grayed out setup/hold zone. figure 33. tx processing in continuous mode note the use of dclk is required when the modula tion shaping is enabled (see section 3.4.5). control spi sync recog. dio1/dclk miso mosi sck nss rx tx/rx data dio2/data dio0 dio3 dio4 dio5 dclk t_data t_data data (nrz)
www.semtech.com page 59 sx1235 wireless & sensing datasheet rev 1 - december 2012 5.4.3. rx processing if the bit synchronizer is disabled, the raw demodulator output is made directly available on data pin and no dclk signal is provided. conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on dio2/data and dio1/dclk pins. data is sampled on the rising edge of dclk and updated on the falling edge as illustrated below. figure 34. rx processing in continuous mode note in continuous mode it is always recommended to enable the bit synchronizer to clean the data signal even if the dclk signal is not used by the uc (bit synchron izer is automatically enabled in packet mode). 5.5. packet mode 5.5.1. general description in packet mode the nrz data to (from) the (de)modulator is no t directly accessed by the uc but stored in the fifo and accessed via the spi interface. in addition, the sx1235 packet hand ler performs several pack et oriented tasks such as preamble and sync word generation, crc calculation/che ck, whitening/dewhitening of data, manchester encoding/decoding, address filtering, etc. this simplifies software and reduces uc overhead by perform ing these repetitive tasks wi thin the rf chip itself. another important feature is ability to fill and empty the fi fo in sleep/stdby mode, ensu ring optimum power consumption and adding more flexib ility for the software. data (nrz) dclk
www.semtech.com page 60 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 35. packet mode conceptual view note the bit synchronizer is automa tically enabled in packet mode. 5.5.2. packet format 5.5.2.1. fixed length packet format fixed length packet format is selected when bit packetformat is set to 0 and payloadlength is set to any value greater than 0. in applications where the packet length is fixed in advance, th is mode of operation december be of interest to minimize rf overhead (no length byte field is required). all nodes, whet her tx only, rx only, or tx/rx should be programmed with the same packet length value. the length of the payload is limited to 2047 bytes. the length programmed in payloadlength relates only to the pa yload which includes the message and the optional address byte. in this mode, the payload must contai n at least one byte, i.e. address or message byte. an illustration of a fixed length packet is shown below. it contains the following fields: ? preamble (1010...) ? sync word (network id) ? optional address byte (node id) ? message data ? optional 2-bytes crc checksum control spi packet handler sync recog. dio1 miso mosi sck nss rx tx data fifo (+sr) dio2 dio0 dio3 dio4 dio5
www.semtech.com page 61 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 36. fixed length packet format 5.5.2.2. variable length packet format variable length packet format is selected when bit packetformat is set to 1. this mode is useful in applications where the length of the pa cket is not known in advance and can vary over time. it is then necessary for the transmitter to send the length information together with each packet in order for the receiver to operate properly. in this mode the length of the payload, indicated by the length byte, is given by the first by te of the fifo and is limited to 255 bytes. note that the length byte itself is not included in its calculation. in this mode, th e payload must contain at least 2 bytes, i.e. length + address or message byte. an illustration of a variable length packet is shown below. it contains the following fields: ? preamble (1010...) ? sync word (network id) ? length byte ? optional address byte (node id) ? message data message up to 2047 bytes address byte crc 2-bytes sync word 0 to 8 bytes payload ( min 1 b y te ) crc checksum calculation fields added by the packet handler in tx and processed and removed in rx optional user provided fields which are part of the payload message part of the payload optional dc free data coding preamble 0 to 65536 bytes
www.semtech.com page 62 sx1235 wireless & sensing datasheet rev 1 - december 2012 ? optional 2-bytes crc checksum figure 37. variable length packet format 5.5.2.3. unlimited length packet format unlimited length packet format is selected when bit packetformat is set to 0 and payloadlength is set to 0. the user can then transmit and receive packet of arbitrary length and payloadlength register is not used in tx/rx modes for counting the length of the bytes transmitted/received. in tx the data is transmitted depending on the txstartcondition bit. on the rx side the data processing features like address filtering, manchester encoding and data whitening are not available if the sync pattern length is set to zero ( syncon = 0 ). the filling of the fifo in this case can be controlled by the bit fifofillcondition . the crc detection in rx is also not supported in this mode of the packet handler, howe ver crc generation in tx is operational. the interrupts like crcok & payloadready are not available either. an unlimited length packet is made up of the following fields: ? preamble (1010...). ? sync word (network id). ? optional address byte (node id). ? message data ? optional 2-bytes crc checksum (tx only) figure 38. unlimited length packet format message up to 255 bytes address byte length byte crc 2-bytes sync word 0 to 8 bytes preamble 0 to 65536 bytes payload (min 2 bytes) crc checksum calculation fields added by the packet handler in tx and processed and removed in rx optional user provided fields which are part of the payload message part of the payload optional dc free data coding message unlimited length address byte sync word 0 to 8 bytes preamble 0 to 65535 bytes payload fields added by the packet handler in tx and processed and removed in rx optional user provided fields which are part of the payload message part of the payload dc free data encoding
www.semtech.com page 63 sx1235 wireless & sensing datasheet rev 1 - december 2012 5.5.3. tx processing in tx mode the packet handler dynamically builds the pa cket by performing the following operations on the payload available in the fifo: ? add a programmable number of preamble bytes ? add a programmable sync word ? optionally calculating crc over complete payload field (optional length byte + optional address byte + message) and appending the 2 bytes checksum. ? optional dc-free encoding of the data (manchester or whitening) only the payload (including optional address and length fi elds) is required to be provided by the user in the fifo. the transmission of packet data is initiated by the packet handler only if the chip is in tx mode and the transmission condition defined by txstartcondition is fulfilled. if transmission condition is not fulfilled then the packet handler transmits a preamble sequence until the cond ition is met. this happens only if the preamble length /= 0, otherwise it transmits a zero or one until the condition is me t to transmit the packet data. the transmission condition itself is defined as: ? if txstartcondition = 1, the packet handler waits until the first byte is written into the fifo, t hen it starts sending the preamble followed by the sync word and user payload ? if txstartcondition = 0, the packet handler waits until the number of bytes written in the fifo is equal to the number defined in regfifothresh + 1 ? if the condition for transmission was alre ady fulfilled i.e. the fifo was filled in sleep/stdby th en the transmission of packet starts immediately on enabling tx 5.5.4. rx processing in rx mode the packet handler extracts the user payl oad to the fifo by performing the following operations: ? receiving the preamble and stripping it off ? detecting the sync word and stripping it off ? optional dc-free decoding of data ? optionally checking the address byte ? optionally checking crc and reflecting the result on crcok. only the payload (including optional address and length fields) is made available in the fifo. when the rx mode is enabled the demodulator receives the pr eamble followed by the detecti on of sync word. if fixed length packet format is enabled then the number of bytes received as the payload is given by the payloadlength parameter. in variable length mode the first byte receiv ed after the sync word is interpreted as the length of the received packet. the internal length counter is initializ ed to this received length. the payloadlength register is set to a value which is greater than the maximum expected length of the received packet. if th e received length is greater than the maximum length stored in payloadlength register the packet is discarded other wise the complete packet is received. if the address check is enabled then the second byte received in case of variable length and first byte in case of fixed length is the address byte. if the address matches to the one in the nodeaddress field, reception of the data continues
www.semtech.com page 64 sx1235 wireless & sensing datasheet rev 1 - december 2012 otherwise it's stopped. the cr c check is performed if crcon = 1 and the result is available in crcok indicating that the crc was successful. an interrupt ( payloadready ) is also generated on dio0 as soon as the payload is available in the fifo. the payload available in the fifo can also be read in sleep/standby mode. if the crc fails the payloadready interrupt is not generated and the fifo is cleared. this function can be overridden by setting crcautoclearoff = 1, forcing the availability of payloadready interrupt and the payload in the fifo even if the crc fails. 5.5.5. handling large packets when payloadlength exceeds fifo size (64 by tes) whether in fixed, variable or unlimited length packet format, in addition to packetsent in tx and payloadready or crcok in rx, the fifo interrupts/flags can be used as described below: ? for tx: fifo can be prefilled in slee p/standby but must be refille d "on-the-fly" during tx wit h the rest of the payload. 1) prefill fifo (in sleep/standby firs t or directly in tx mode) until fifothreshold or fifofull is set 2) in tx, wait for fifothreshold or fifoempty to be set (i.e. fifo is nearly empty) 3) write bytes into the fifo until fifothreshold or fifofull is set. 4) continue to step 2 until the entire message has been written to the fifo ( packetsent will fire when the last bit of the packet has been sent). ? for rx: fifo must be unfilled "on-the-fly" during rx to prev ent fifo overrun. 1) start reading bytes from the fifo when fifoempty is cleared or fifothreshold becomes set. 2) suspend reading from the fifo if fifoempty fires before all bytes of the message have been read 3) continue to step 1 until payloadready or crcok fires 4) read all remaining bytes from the fifo either in rx or sleep/standby mode 5.5.6. packet filtering the sx1235 packet handler offers several mechanisms for pack et filtering, ensuring that only useful packets are made available to the uc, reducing significantly system power consumption and software complexity. 5.5.6.1. sync word based sync word filtering/recognition is used for identifying the start of the paylo ad and also for network identification. as previously described, the sync word recognit ion block is configured (size, value) in regsyncconfig and regsyncvalue(i) registers. this information is used, both for appendi ng sync word in tx, and filtering packets in rx. every received packet which does not st art with this locally config ured sync word is autom atically discarded and no interrupt is generated. when the sync word is detected, payloa d reception automatically starts and syncaddressmatch is asserted. note sync word values containing 0x00 byte(s) are forbidden 5.5.6.2. address based address filtering can be enabled via the addressfiltering bits. it adds another level of filt ering, above sync word (i.e. sync must match first), typically useful in a multi-node networks where a network id is shared between all nodes (sync word) and each node has its own id (address).
www.semtech.com page 65 sx1235 wireless & sensing datasheet rev 1 - december 2012 two address based filtering options are available: ? addressfiltering = 01 : received address field is compared with internal register nodeaddress . if they match then the packet is accepted and processed, otherwise it is discarded. ? addressfiltering = 10 : received address field is compared with internal registers nodeaddress and broadcastaddress . if either is a match, the received packet is accepted and proc essed, otherwise it is discar ded. this additional check with a constant is useful for implementing broadcast in a multi-node networks please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in the fifo. in addition, nodeaddress and addressfiltering only apply to rx. on tx side, if address filtering is expected, the address byte should simply be put into the fifo like any other byte of the payload. as address filtering requires a sync word match, both features share th e same interrupt flag syncaddressmatch . 5.5.6.3. length based in variable length packet mode, payloadlength must be programmed with the maxi mum payload length permitted. if received length byte is smaller than this maximum then th e packet is accepted and processed, otherwise it is discarded. please note that the received le ngth byte, as part of the payload, is not stri pped off the packet and is made available in the fifo. to disable this function the user should set the value of the payloadlength to 2047. 5.5.6.4. crc based the crc check is enabled by setting bit crcon in regpacketconfig1 . it is used for checking the integrity of the message. ? on tx side a two byte crc checksum is calculated on th e payload part of the packet and appended to the end of the message ? on rx side the checksum is calculated on the received pa yload and compared with the two checksum bytes received. the result of the comparison is stored in bit crcok. by default, if the crc check fails then the fifo is automatically cleared and no inte rrupt is generated. this filtering functio n can be disabled via crcautoclearoff bit and in this case, even if crc fa ils, the fifo is not cleared and only payloadready interrupt goes high. please note that in both cases, the two crc checksum bytes ar e stripped off by the packet handler and only the payload is made available in the fifo. two crc implementations are selected with bit crcwhiteningtype . table 31 crc description a c code implementation of each crc type is proposed in application section 7. crc type crcwhiteningtype polynomial seed value complemented ccitt 0 (default) x 16 + x 12 + x 5 + 1 0x1d0f yes ibm 1 x 16 + x 15 + x 2 + 1 0xffff no
www.semtech.com page 66 sx1235 wireless & sensing datasheet rev 1 - december 2012 5.5.7. dc-free data mechanisms the payload to be transmitted december contain long sequ ences of 1's and 0's, which introduces a dc bias in the transmitted signal. the radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth. it also introduces data dependencies in the normal operation of the demodulator. thus it is useful if the transmitted data is random and dc free. for such purposes, two techniques are made available in th e packet handler: manchester encoding and data whitening. note only one of the two methods can be enabled at a time. 5.5.7.1. manc hester encoding manchester encoding/decoding is enabled if dcfree = 01 and can only be used in packet mode. the nrz data is converted to manchester code by coding '1' as "10" and '0' as "01". in this case, the maximum chip rate is th e maximum bit rate given in the specificatio ns section and the actual bit rate is half the chip rate. manchester encoding and decoding is only applied to the payload and crc checksum while preamble and sync word are kept nrz. however, the chip rate from preamble to crc is the same and defined by bitrate in regbitrate (chip rate = bit rate nrz = 2 x bit rate manchester). manchester encoding/dec oding is thus made transparent for the user, who still provides/retrieves nrz data to/from the fifo. figure 39. manchester encoding/decoding ...sync payload... rf chips @ br ... 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 ... user/nrz bits manchester off ... 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 ... user/nrz bits manchester on ... 1 1 1 0 1 0 0 1 0 0 1 1 ... t 1/br 1/br
www.semtech.com page 67 sx1235 wireless & sensing datasheet rev 1 - december 2012 5.5.7.2. data whitening another technique called whitening or scrambling is widely us ed for randomizing the user data before radio transmission. the data is whitened using a random sequence on the tx side and de-whitened on the rx side using the same sequence. comparing to manchester technique it has the advantage of ke eping nrz data rate i.e. actual bit rate is not halved. the whitening/de-whitening process is enabled if dcfree = 10 . a 9-bit lfsr is used to generate a random sequence. the payload and 2-byte crc checksum is then xored with this random sequence as shown belo w. the data is de-whitened on the receiver side by xoring with the same random sequence. payload whitening/de-white ning is thus made transparent for the user, who still provides/r etrieves nrz data to/from the fifo. figure 40. data whitening polynomial 5.5.8. beacon tx mode in some short range wireless network topologies a repetitive message, also known as beacon, is transmitted periodically by a transmitter. the beacon tx mode allows for the re-transmissi on of the same packet wit hout having to fill the fifo multiple times with the same data. when beaconon in regpacketconfig2 is set to 1, the fifo can be filled only once in sleep or stdby mode with the required payload. after a first transmission, fifoempty will go high as usual, but the fifo content will be restored when the chip exits transmit mode. fifoempty , fifofull and fifolevel flags are also restored. this feature is only available in fixed packet format, with t he payload length smaller than the fifo size. the control of the chip modes (tx-sleep-tx....) can either be undertaken by the microcontroller, or be automated in the top sequencer. see example in section 5.5.8. the beacon tx mode is exited by setting beaconon to 0, and clearing the fifo by setting fifooverrun to 1. 5.6. io-homecontrol ? compatibility mode the sx1235 features a io-homecontrol ? compatibility mode. please contact your local semtech repres entative for details on its implementation. x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x 8 lfsr polynomial =x 9 + x 5 + 1 transmit data whitened data
www.semtech.com page 68 sx1235 wireless & sensing datasheet rev 1 - december 2012 6. description of the registers 6.1. register table summary table 32 registers summary address register name reset (built-in) default (recom mended) description 0x00 regfifo 0x00 fifo read/write access 0x01 regopmode 0x01 operating modes of the transceiver 0x02 regbitratemsb 0x1a bit rate setting, most significant bits 0x03 regbitratelsb 0x0b bit rate setting, least significant bits 0x04 regfdevmsb 0x00 frequency deviation setting, most significant bits 0x05 regfdevlsb 0x52 frequency deviation setting, least significant bits 0x06 regfrfmsb 0xe4 rf carrier frequency, most significant bits 0x07 regfrfmid 0xc0 rf carrier frequency, intermediate bits 0x08 regfrflsb 0x00 rf carrier frequency, least significant bits 0x09 regpaconfig 0x0f pa selection and output power control 0x0a regparamp 0x19 control of the pa ramp time in fsk, low phase noise pll 0x0b regocp 0x2b over current protection control 0x0c reglna 0x20 lna settings 0x0d regrxconfig 0x08 0x0e control of the afc, agc, collision detector 0x0e regrssiconfig 0x02 rssi-related settings 0x0f regrssicollision 0x0a rssi setting of the collision detector 0x10 regrssithresh 0xff rssi threshold control 0x11 regrssivalue - rssi value in dbm 0x12 regrxbw 0x15 channel filter bw control 0x13 regafcbw 0x0b channel filter bw control during the afc 0x14 regookpeak 0x28 ook demodulator selection and control in peak mode 0x15 regookfix 0x0c fixed threshold control of the ook demodulator 0x16 regookavg 0x12 average threshold control of the ook demodulator 0x17 reserved17 0x47 - 0x18 reserved18 0x32 - 0x19 reserved19 0x3e -
www.semtech.com page 69 sx1235 wireless & sensing datasheet rev 1 - december 2012 0x1a regafcfei 0x00 afc and fei control 0x1b regafcmsb 0x00 msb of the frequency correction of the afc 0x1c regafclsb 0x00 lsb of the frequency correction of the afc 0x1d regfeimsb 0x00 msb of the calculated frequency error 0x1e regfeilsb 0x00 lsb of the calculated frequency error 0x1f regpreambledetect 0x40 0xaa settings of the preamble detector 0x20 regrxtimeout1 0x00 timeout duration between rx request and rssi detection 0x21 regrxtimeout2 0x00 timeout duration between rssi detection and payloadready 0x22 regrxtimeout3 0x00 timeout duration between rssi and syncaddress 0x23 regrxdelay 0x00 delay between rx cycles 0x24 regosc 0x05 0x07 rc oscillators settings, clkout frequency 0x25 regpreamblemsb 0x00 preamble length, msb 0x26 regpreamblelsb 0x03 preamble length, lsb 0x27 regsyncconfig 0x93 sync word recognition control 0x28-0x2f regsyncvalue1-8 0x55 0x01 sync word bytes, 1 through 8 0x30 regpacketconfig1 0x90 packet mode settings 0x31 regpacketconfig2 0x40 packet mode settings 0x32 regpayloadlength 0x40 payload length setting 0x33 regnodeadrs 0x00 node address 0x34 regbroadcastadrs 0x00 broadcast address 0x35 regfifothresh 0x0f 0x8f fifo threshold, tx start condition 0x36 regseqconfig1 0x00 top level sequencer settings 0x37 regseqconfig2 0x00 top level sequencer settings 0x38 regtimerresol 0x00 timer 1 and 2 resolution control 0x39 regtimer1coef 0xf5 timer 1 setting 0x3a regtimer2coef 0x20 timer 2 setting 0x3b regimagecal 0x82 0x02 image calibration engine control 0x3c regtemp - temperature sensor value 0x3d reglowbat 0x02 low battery indicator settings address register name reset (built-in) default (recom mended) description
www.semtech.com page 70 sx1235 wireless & sensing datasheet rev 1 - december 2012 note - reset values are auto matically refreshed in the chip at power on reset - default values are the semtech recommended regi ster values, optimizing the device operation - registers for which the default value differs from the rese t value are denoted by a * in the tables of section 6.2 0x3e regirqflags1 0x80 status register: pll lock state, timeout, rssi > threshold... 0x3f regirqflags2 0x40 status register: fifo handling flags, low battery detection... 0x40 regdiomapping1 0x00 mapping of pins dio0 to dio3 0x41 regdiomapping2 0x00 mapping of pins dio4 and dio5, clkout frequency 0x42 regversion 0x21 semtech id relating the silicon revision 0x43 regagcref 0x13 adjustment of the agc thresholds 0x44 regagcthresh1 0x0e 0x45 regagcthresh2 0x5b 0x46 regagcthresh3 0xdb 0x4b regpllhop 0x2e control the fast frequency hopping mode 0x58 regtcxo 0x09 tcxo or xtal input setting 0x5a regpadac 0x84 higher power settings of the pa 0x5c regpll 0xd0 control of the pll bandwidth 0x5e regplllowpn 0xd0 control of the low phase noise pll bandwidth 0x5f regpllgopt 0x32 0x37 integrator loop gain control (category 1 use only) 0x6c regformertemp - stored temperature during the former iq calibration 0x70 regbitratefrac 0x00 fractional part in the bit rate division ratio 0x42 + regtest - internal test registers. do not overwrite address register name reset (built-in) default (recom mended) description
www.semtech.com page 71 sx1235 wireless & sensing datasheet rev 1 - december 2012 6.2. register map convention: r: read, w: write, t:trigger, c: clear table 33 register map name (address) bits variable name mode default value description regfifo (0x00) 7-0 fifo rw 0x00 fifo data input/output resisters for common settings regopmode (0x01) 7 unused r 0x00 unused 6-5 modulationtype rw 0x00 modulation scheme: 00 ? fsk 01 ? ook 10 -11 ? reserved 4-3 modulationshaping rw 0x00 data shaping: in fsk: 00 ? no shaping 01 ? gaussian filter bt = 1.0 10 ? gaussian filter bt = 0.5 11 ? gaussian filter bt = 0.3 in ook: 00 ? no shaping 01 ? filtering with f cutoff = bit_rate 10 ? filtering with f cutoff = 2*bit_rate (for bit_rate < 125 kb/s) 11 ? reserved 2-0 mode rw 0x01 transceiver modes 000 ? sleep mode 001 ? stdby mode 010 ? fs mode tx (fstx) 011 ? transmitter mode (tx) 100 ? fs mode rx (fsrx) 101 ? receiver mode (rx) 110 ? reserved 111 ? reserved regbitratemsb (0x02) 7-0 bitrate(15:8) rw 0x1a msb of bit rate (chip rate if manchester encoding is enabled) regbitratelsb (0x03) 7-0 bitrate(7:0) rw 0x0b lsb of bit rate (chip rate if manchester encoding is enabled) default value: 4.8 kb/s regfdevmsb (0x04) 7-6 unused r 0x00 unused 5-0 fdev(13:8) rw 0x00 msb of the frequency deviation regfdevlsb (0x05) 7-0 fdev(7:0) rw 0x52 lsb of the frequency deviation default value: 5 khz bitrate fxosc bitrate 15 0 (,) bitratefrac 16 ------------------------------- + ------------------------------------------------------------------------- = fdev fstep fdev 15 0 (,) =
www.semtech.com page 72 sx1235 wireless & sensing datasheet rev 1 - december 2012 regfrfmsb (0x06) 7-0 frf(23:16) rw 0xe4 msb of the rf carrier frequency regfrfmid (0x07) 7-0 frf(15:8) rw 0xc0 msb of the rf carrier frequency regfrflsb (0x08) 7-0 frf(7:0) rw 0x00 lsb of rf carrier frequency default value: 915.000 mhz the rf frequency is taken into account internally only when: - entering fsrx/fstx modes - re-starting the receiver registers for the transmitter regpaconfig (0x09) 7 paselect rw 0x00 selects pa output pin 0 ? rfo pin. maximum power of +13 dbm 1 ? pa_boost pin. maximum power of +20 dbm 6-4 unused r 0x00 unused 3-0 outputpower rw 0x0f output power setting, with 1db steps pout = 2 + outputpower [dbm], on pa_boost pin pout = -1 + outputpower [dbm], on rfo pin regparamp (0x0a) 7-5 unused r - unused 4 lowpntxplloff rw 0x01 select a higher power, lower phase noise pll only when the transmitter is used: 0 ? standard pll used in rx mode, lower pn pll in tx 1 ? standard pll used in both tx and rx modes 3-0 paramp rw 0x09 rise/fall time of ramp up/down in fsk 0000 ? 3.4 ms 0001 ? 2 ms 0010 ? 1 ms 0011 ? 500 us 0100 ? 250 us 0101 ? 125 us 0110 ? 100 us 0111 ? 62 us 1000 ? 50 us 1001 ? 40 us (d) 1010 ? 31 us 1011 ? 25 us 1100 ? 20 us 1101 ? 15 us 1110 ? 12 us 1111 ? 10 us name (address) bits variable name mode default value description frf fstep frf 23 0 ; () =
www.semtech.com page 73 sx1235 wireless & sensing datasheet rev 1 - december 2012 regocp (0x0b) 7-6 unused r 0x00 unused 5 ocpon rw 0x01 enables overload current protection (ocp) for the pa: 0 ? ocp disabled 1 ? ocp enabled 4-0 ocptrim rw 0x0b trimming of ocp current: i max = 45+5*ocptrim [ma] if ocptrim <= 15 (120 ma) / i max = -30+10*ocptrim [ma] if 15 < ocptrim <= 27 (130 to 240 ma) i max = 240ma for higher settings default i max = 100ma registers for the receiver reglna (0x0c) 7-5 lnagain rw 0x01 lna gain setting: 000 ? reserved 001 ? g1 = highest gain 010 ? g2 = highest gain ? 6 db 011 ? g3 = highest gain ? 12 db 100 ? g4 = highest gain ? 24 db 101 ? g5 = highest gain ? 36 db 110 ? g6 = highest gain ? 48 db 111 ? reserved note: reading this address always returns the current lna gain (which december be different from what had been previously selected if agc is enabled. 4-2 - r 0x00 unused 1-0 lnaboost rw 0x00 improves the system noise figure at the expense of rx current consumption: 00 ? default setting, meeting the specification 11 ? improved sensitivity regrxconfig (0x0d) 7 restartrxoncollision rw 0x00 turns on the mechanism restarting the receiver automatically if it gets saturated or a packet collision is detected 0 ? no automatic restart 1 ? automatic restart on 6 restartrxwithoutplllock wt 0x00 triggers a manual restart of the receiver chain when set to 1. use this bit when there is no frequency change, restartrxwithplllock otherwise. 5 restartrxwithplllock wt 0x00 triggers a manual restart of the receiver chain when set to 1. use this bit when there is a frequency change, requiring some time for the pll to re-lock. 4 afcautoon rw 0x00 0 ? no afc performed at receiver startup 1 ? afc is performed at each receiver startup 3 agcautoon rw 0x01 0 ? lna gain forced by the lnagain setting 1 ? lna gain is controlled by the agc 2-0 rxtrigger rw 0x06 * selects the event triggering agc and/or afc at receiver startup. see table 24 for a description. name (address) bits variable name mode default value description
www.semtech.com page 74 sx1235 wireless & sensing datasheet rev 1 - december 2012 regrssiconfig (0x0e) 7-3 rssioffset rw 0x00 signed rssi offset, to compensate for the possible losses/ gains in the front-end (lna, saw filter...) 1db / lsb, 2?s complement format 2-0 rssismoothing rw 0x02 defines the number of samples taken to average the rssi result: 000 ? 2 samples used 001 ? 4 samples used 010 ? 8 samples used 011 ? 16 samples used 100 ? 32 samples used 101 ? 64 samples used 110 ? 128 samples used 111 ? 256 samples used regrssicollision (0x0f) 7-0 rssicollisionthreshold rw 0x0a sets the threshold used to consider that an interferer is detected, witnessing a packet collision. 1db/lsb (only rssi increase) default: 10db regrssithresh (0x10) 7-0 rssithreshold rw 0xff rssi trigger level for the rssi interrupt: - rssithreshold / 2 [dbm] regrssivalue (0x11) 7-0 rssivalue r - absolute value of the rssi in dbm, 0.5db steps. rssi = - rssivalue/2 [dbm] regrxbw (0x12) 7 unused r - unused 6-5 reserved rw 0x00 reserved 4-3 rxbwmant rw 0x02 channel filter bandwidth control: 00 ? rxbwmant = 16 10 ? rxbwmant = 24 01 ? rxbwmant = 20 11 ? reserved 2-0 rxbwexp rw 0x05 channel filter bandwidth control: fsk mode: regafcbw (0x13) 7-5 reserved rw 0x00 reserved 4-3 rxbwmantafc rw 0x01 rxbwmant parameter used during the afc 2-0 rxbwexpafc rw 0x03 rxbwexp parameter used during the afc name (address) bits variable name mode default value description rxbw fxosc rxbwmant 2 rxbwexp 2 + ----------------------------------------------------------------- - =
www.semtech.com page 75 sx1235 wireless & sensing datasheet rev 1 - december 2012 regookpeak (0x14) 7-6 reserved rw 0x00 reserved 5 bitsyncon rw 0x01 enables the bit synchronizer. 0 ? bit sync disabled (not possible in packet mode) 1 ? bit sync enabled 4-3 ookthreshtype rw 0x01 selects the type of threshold in the ook data slicer: 00 ? fixed threshold 10 ? average mode 01 ? peak mode (default) 11 ? reserved 2-0 ookpeaktheshstep rw 0x00 size of each decrement of the rssi threshold in the ook demodulator: 000 ? 0.5 db 001 ? 1.0 db 010 ? 1.5 db 011 ? 2.0 db 100 ? 3.0 db 101 ? 4.0 db 110 ? 5.0 db 111 ? 6.0 db regookfix (0x15) 7-0 ookfixedthreshold rw 0x0c fixed threshold for the data slicer in ook mode floor threshold for the data slicer in ook when peak mode is used regookavg (0x16) 7-5 ookpeakthreshdec rw 0x00 period of decrement of the rssi threshold in the ook demodulator: 000 ? once per chip 001 ? once every 2 chips 010 ? once every 4 chips 011 ? once every 8 chips 100 ? twice in each chip 101 ? 4 times in each chip 110 ? 8 times in each chip 111 ? 16 times in each chip 4 reserved rw 0x01 reserved 3-2 ookaverageoffset rw 0x00 static offset added to the threshold in average mode in order to reduce glitching activity (ook only): 00 ? 0.0 db 10 ? 4.0 db 01 ? 2.0 db 11 ? 6.0 db 1-0 ookaveragethreshfilt rw 0x02 filter coefficients in average mode of the ook demodulator: 00 ? f c chip rate / 32. 01 ? f c chip rate / 8. 10 ? f c chip rate / 4. 11 ? f c chip rate / 2. regres17 to regres19 7-0 reserved rw 0x47 0x32 0x3e reserved. keep the reset values. regafcfei (0x1a) 7-5 unused r - unused 4 agcstart wt 0x00 triggers an agc sequence when set to 1. 3 reserved rw 0x00 reserved 2 unused - - unused 1 afcclear wc 0x00 clear afc register set in rx mode. always reads 0. 0 afcautoclearon rw 0x00 only valid if afcautoon is set 0 ? afc register is not cleared at the beginning of the automatic afc phase 1 ? afc register is cleared at the beginning of the automatic afc phase name (address) bits variable name mode default value description
www.semtech.com page 76 sx1235 wireless & sensing datasheet rev 1 - december 2012 regafcmsb (0x1b) 7-0 afcvalue(15:8) rw 0x00 msb of the afcvalue, 2?s complement format. can be used to overwrite the current afc value regafclsb (0x1c) 7-0 afcvalue(7:0) rw 0x00 lsb of the afcvalue, 2?s complement format. can be used to overwrite the current afc value regfeimsb (0x1d) 7-0 feivalue(15:8) rw - msb of the measured frequency offset, 2?s complement. must be read before regfeilsb. regfeilsb (0x1e) 7-0 feivalue(7:0) rw - lsb of the measured frequency offset, 2?s complement frequency error = feivalue x fstep regpreambledete ct (0x1f) 7 preambledetectoron rw 0x01 * enables preamble detector when set to 1. the agc settings supersede this bit during the startup / agc phase. 0 ? turned off 1 ? turned on 6-5 preambledetectorsize rw 0x01 * number of preamble bytes to detect to trigger an interrupt 00 ? 1 byte 10 ? 3 bytes 01 ? 2 bytes 11 ? reserved 4-0 preambledetectortol rw 0x0a * number or chip errors tolerated over preambledetectorsize. 4 chips per bit. regrxtimeout1 (0x20) 7-0 timeoutrxrssi rw 0x00 timeout interrupt is generated timeoutrxrssi *16*t bit after switching to rx mode if rssi interrupt doesn?t occur (i.e. rssivalue > rssithreshold) 0x00: timeoutrxrssi is disabled regrxtimeout2 (0x21) 7-0 timeoutrxpreamble rw 0x00 timeout interrupt is generated timeoutrxpreamble *16*t bit after switching to rx mode if preamble interrupt doesn?t occur 0x00: timeoutrxpreamble is disabled regrxtimeout3 (0x22) 7-0 timeoutsignalsync rw 0x00 timeout interrupt is generated timeoutsignalsync *16*t bit after the rx mode is programmed, if syncaddress doesn?t occur 0x00: timeoutsignalsync is disabled regrxdelay (0x23) 7-0 interpacketrxdelay rw 0x00 additional delay befopre an automatic receiver restart is launched: delay = interpacke trxdelay*4*tbit rc oscillator registers regosc (0x24) 7-4 unused r - unused 3 rccalstart wt 0x00 triggers the calibration of the rc oscillator when set. always reads 0. rc calibration must be triggered in standby mode. 2-0 clkout rw 0x07 * selects clkout frequency: 000 ? fxosc 001 ? fxosc / 2 010 ? fxosc / 4 011 ? fxosc / 8 100 ? fxosc / 16 101 ? fxosc / 32 110 ? rc (automatically enabled) 111 ? off name (address) bits variable name mode default value description
www.semtech.com page 77 sx1235 wireless & sensing datasheet rev 1 - december 2012 packet handling registers regpreamblemsb (0x25) 7-0 preamblesize(15:8) rw 0x00 size of the preamble to be sent (from txstartcondition fulfilled). (msb byte) regpreamblelsb (0x26) 7-0 preamblesize(7:0) rw 0x03 size of the preamble to be sent (from txstartcondition fulfilled). (lsb byte) regsyncconfig (0x27) 7-6 autorestartrxmode rw 0x02 controls the automatic restart of the receiver after the reception of a valid packet (payloadready or crcok): 00 ? off 01 ? on, without waiting for the pll to re-lock 10 ? on, wait for the pll to lock (frequency changed) 11 ? reserved 5 preamblepolarity rw 0x00 sets the polarity of the preamble 0 ? 0xaa (default) 1 ? 0x55 4 syncon rw 0x01 enables the sync word generation and detection: 0 ? off 1 ? on 3 fifofillcondition rw 0x00 fifo filling condition: 0 ? if syncaddress interrupt occurs 1 ? as long as fifofillcondition is set 2-0 syncsize rw 0x03 size of the sync word: ( syncsize + 1) bytes, ( syncsize ) bytes if iohomeon =1 regsyncvalue1 (0x28) 7-0 syncvalue(63:56) rw 0x01 * 1 st byte of sync word. (msb byte) used if syncon is set. regsyncvalue2 (0x29) 7-0 syncvalue(55:48) rw 0x01 * 2 nd byte of sync word used if syncon is set and (syncsize +1) >= 2. regsyncvalue3 (0x2a) 7-0 syncvalue(47:40) rw 0x01 * 3 rd byte of sync word. used if syncon is set and (syncsize +1) >= 3. regsyncvalue4 (0x2b) 7-0 syncvalue(39:32) rw 0x01 * 4 th byte of sync word. used if syncon is set and (syncsize +1) >= 4. regsyncvalue5 (0x2c) 7-0 syncvalue(31:24) rw 0x01 * 5 th byte of sync word. used if syncon is set and (syncsize +1) >= 5. regsyncvalue6 (0x2d) 7-0 syncvalue(23:16) rw 0x01 * 6 th byte of sync word. used if syncon is set and (syncsize +1) >= 6. regsyncvalue7 (0x2e) 7-0 syncvalue(15:8) rw 0x01 * 7 th byte of sync word. used if syncon is set and (syncsize +1) >= 7. regsyncvalue8 (0x2f) 7-0 syncvalue(7:0) rw 0x01 * 8 th byte of sync word. used if syncon is set and (syncsize +1) = 8. name (address) bits variable name mode default value description
www.semtech.com page 78 sx1235 wireless & sensing datasheet rev 1 - december 2012 regpacketconfig1 (0x30) 7 packetformat rw 0x01 defines the packet format used: 0 ? fixed length 1 ? variable length 6-5 dcfree rw 0x00 defines dc-free encoding/decoding performed: 00 ? none (off) 01 ? manchester 10 ? whitening 11 ? reserved 4 crcon rw 0x01 enables crc calculation/check (tx/rx): 0 ? off 1 ? on 3 crcautoclearoff rw 0x00 defines the behavior of the packet handler when crc check fails: 0 ? clear fifo and restart new packet reception. no payloadready interrupt issued. 1 ? do not clear fifo. payloadready interrupt issued. 2-1 addressfiltering rw 0x00 defines address based filtering in rx: 00 ? none (off) 01 ? address field must match nodeaddress 10 ? address field must match nodeaddress or broadcastaddress 11 ? reserved 0 crcwhiteningtype rw 0x00 selects the crc and whitening algorithms: 0 ? ccitt crc implementation with standard whitening 1 ? ibm crc implementation with alternate whitening regpacketconfig2 (0x31) 7 unused r - unused 6 datamode rw 0x01 data processing mode: 0 ? continuous mode 1 ? packet mode 5 iohomeon rw 0x00 enables the io-homecontrol ? compatibility mode 0 ? disabled 1 ? enabled 4 iohomepowerframe rw 0x00 reserved - linked to io-homecontrol ? compatibility mode 3 beaconon rw 0x00 enables the beacon mode in fixed packet format 2-0 payloadlength(10:8) rw 0x00 packet length most significant bits regpayloadlength (0x32) 7-0 payloadlength(7:0) rw 0x40 if packetformat = 0 (fixed), payload length. if packetformat = 1 (variable), max length in rx, not used in tx. regnodeadrs (0x33) 7-0 nodeaddress rw 0x00 node address used in address filtering. regbroadcastadrs (0x34) 7-0 broadcastaddress rw 0x00 broadcast address used in address filtering. name (address) bits variable name mode default value description
www.semtech.com page 79 sx1235 wireless & sensing datasheet rev 1 - december 2012 regfifothresh (0x35) 7 txstartcondition rw 0x01 * defines the condition to start packet transmission: 0 ? fifolevel (i.e. the number of bytes in the fifo exceeds fifothreshold) 1 ? fifoempty goes low (i.e. at least one byte in the fifo) 6 unused r - unused 5-0 fifothreshold rw 0x0f used to trigger fifolevel interrupt, when: number of bytes in fifo >= fifothreshold + 1 sequencer registers regseqconfig1 (0x36) 7 sequencerstart wt 0x00 controls the top level sequencer when set to ?1?, executes the ?start? transition. the sequencer can only be enabled when the chip is in sleep or standby mode. 6 sequencerstop wt 0x00 forces the sequencer off. always reads ?0? 5 idlemode rw 0x00 selects chip mode during the state: 0: standby mode 1: sleep mode 4-3 fromstart rw 0x00 controls the sequencer transition when sequencerstart is set to 1 in sleep or standby mode: 00: to lowpowerselection 01: to receive state 10: to transmit state 11: to transmit state on a fifolevel interrupt 2 lowpowerselection rw 0x00 selects the sequencer lowpower state after a to lowpowerselection transition: 0: sequenceroff state with chip on initial mode 1: idle state with chip on standby or sleep mode depending on idlemode note: initial mode is the chip lowpower mode at sequencer start. 1 fromidle rw 0x00 controls the sequencer transition from the idle state on a t1 interrupt: 0: to transmit state 1: to receive state 0 fromtransmit rw 0x00 controls the sequencer transition from the transmit state: 0: to lowpowerselection on a packetsent interrupt 1: to receive state on a packetsent interrupt name (address) bits variable name mode default value description
www.semtech.com page 80 sx1235 wireless & sensing datasheet rev 1 - december 2012 regseqconfig2 (0x37) 7-5 fromreceive rw 0x00 controls the sequencer transition from the receive state 000 and 111: unused 001: to packetreceived state on a payloadready interrupt 010: to lowpowerselection on a payloadready interrupt 011: to packetreceived state on a crcok interrupt (1) 100: to sequenceroff state on a rssi interrupt 101: to sequenceroff state on a syncaddress interrupt 110: to sequenceroff state on a preambledetect interrupt irrespective of this setting, transition to lowpowerselection on a t2 interrupt (1) if the crc is wrong (corrupted packet, with crc on but crcautoclearon =0), the payloadready interrupt will drive the sequencer to rxtimeout state. 4-3 fromrxtimeout rw 0x00 controls the state-machine transition from the receive state on a rxtimeout interrupt (and on payloadready if fromreceive = 011): 00: to receive state, via receiverestart 01: to transmit state 10: to lowpowerselection 11: to sequenceroff state note: rxtimeout interrupt is a timeoutrxrssi, timeoutrxpreamble or timeoutsignalsync interrupt 2-0 frompacketreceived rw 0x00 controls the state-machine transition from the packetreceived state: 000: to sequenceroff state 001: to transmit state on a fifoempty interrupt 010: to lowpowerselection 011: to receive via fs mode, if frequency was changed 100: to receive state (no frequency change) regtimerresol (0x38) 7-4 unused r - unused 3-2 timer1resolution rw 0x00 resolution of timer 1 00: timer1 disabled 01: 64 us 10: 4.1 ms 11: 262 ms 1-0 timer2resolution rw 0x00 resolution of timer 2 00: timer2 disabled 01: 64 us 10: 4.1 ms 11: 262 ms regtimer1coef (0x39) 7-0 timer1coefficient rw 0xf5 multiplying coefficient for timer 1 regtimer2coef (0x3a) 7-0 timer2coefficient rw 0x20 multiplying coefficient for timer 2 name (address) bits variable name mode default value description
www.semtech.com page 81 sx1235 wireless & sensing datasheet rev 1 - december 2012 services registers regimagecal (0x3b) 7 autoimagecalon rw 0x00 * controls the image calibration mechanism 0 ? calibration of the receiver depending on the temperature is disabled 1 ? calibration of the receiver depending on the temperature enabled. 6 imagecalstart wt - triggers the iq and rssi calibration when set in standby mode. 5 imagecalrunning r 0x00 set to 1 while the image and rssi calibration are running. toggles back to 0 when the process is completed 4 unused r - unused 3 tempchange r 0x00 irq flag witnessing a temperature change exceeding tempthreshold since the last image and rssi calibration: 0 ? temperature change lower than tempthreshold 1 ? temperature change greater than tempthreshold 2-1 te m p t h r e s h o l d rw 0x01 temperature change threshold to trigger a new i/q calibration 00 ? 5 c 01 ? 10 c 10 ? 15 c 11 ? 20 c 0 tempmonitoroff rw 0x00 controls the temperature monitor operation: 0 ? temperature monitoring done in all modes except sleep and standby 1 ? temperature monitoring stopped. regtemp (0x3c) 7-0 te m p va l u e r - measured temperature -1c per lsb needs calibration for absolute accuracy reglowbat (0x3d) 7-4 unused r - unused 3 lowbaton rw 0x00 low battery detector enable signal 0 ? lowbat detector disabled 1 ? lowbat detector enabled 2-0 lowbattrim rw 0x02 trimming of the lowbat threshold: 000 ? 1.695 v 001 ? 1.764 v 010 ? 1.835 v (d) 011 ? 1.905 v 100 ? 1.976 v 101 ? 2.045 v 110 ? 2.116 v 111 ? 2.185 v status registers name (address) bits variable name mode default value description
www.semtech.com page 82 sx1235 wireless & sensing datasheet rev 1 - december 2012 regirqflags1 (0x3e) 7 modeready r - set when the operation mode requested in mode , is ready - sleep: entering sleep mode - standby: xo is running - fs: pll is locked - rx: rssi sampling starts - tx: pa ramp-up completed cleared when changing the operating mode. 6 rxready r - set in rx mode, after rssi, agc and afc. cleared when leaving rx. 5 txready r - set in tx mode, after pa ramp-up. cleared when leaving tx. 4 plllock r - set (in fs, rx or tx) when the pll is locked. cleared when it is not. 3 rssi rwc - set in rx when the rssivalue exceeds rssithreshold. cleared when leaving rx or setting this bit to 1. 2 timeout r - set when a timeout occurs cleared when leaving rx or fifo is emptied. 1 preambledetect rwc - set when the preamble detector has found valid preamble. bit clear when set to 1 0 syncaddressmatch rwc - set when sync and address (if enabled) are detected. cleared when leaving rx or fifo is emptied. this bit is read only in packet mode, rwc in continuous mode regirqflags2 (0x3f) 7 fifofull r - set when fifo is full (i.e. contains 66 bytes), else cleared. 6 fifoempty r - set when fifo is empty, and cleared when there is at least 1 byte in the fifo. 5 fifolevel r - set when the number of bytes in the fifo strictly exceeds fifothreshold , else cleared. 4 fifooverrun rwc - set when fifo overrun occurs. (except in sleep mode) flag(s) and fifo are cleared when this bit is set. the fifo then becomes immediately available for the next transmission / reception. 3 packetsent r - set in tx when the complete packet has been sent. cleared when exiting tx 2 payloadready r - set in rx when the payload is ready (i.e. last byte received and crc, if enabled and crcautoclearoff is cleared , is ok). cleared when fifo is empty. 1 crcok r - set in rx when the crc of the payload is ok. cleared when fifo is empty. 0 lowbat rwc - set when the battery voltage drops below the low battery threshold. cleared only when set to 1 by the user. io control registers name (address) bits variable name mode default value description
www.semtech.com page 83 sx1235 wireless & sensing datasheet rev 1 - december 2012 regdiomapping1 (0x40) 7-6 dio0mapping rw 0x00 mapping of pins dio0 to dio5 see table 29 for mapping in continuous mode see table 30 for mapping in packet mode 5-4 dio1mapping rw 0x00 3-2 dio2mapping rw 0x00 1-0 dio3mapping rw 0x00 regdiomapping2 (0x41) 7-6 dio4mapping rw 0x00 5-4 dio5mapping rw 0x00 3-1 reserved rw 0x00 reserved. retain default value 0 mappreambledetect rw 0x00 allows the mapping of either rssi or preambledetect to the dio pins, as summarized on table 29 and table 30 0 ? rssi interrupt 1 ? preambledetect interrupt version register regversion (0x42) 7-0 version r 0x21 version code of the chip. bits 7-4 give the full revision number; bits 3-0 give the metal mask revision number. additional registers regagcref (0x43) 7-6 unused r - unused 5-0 agcreferencelevel rw 0x13 sets the floor reference for all agc thresholds: agc reference[dbm]= -174dbm+10*log(2* rxbw )+snr+ agcreferencelevel snr = 8db, fixed value regagcthresh1 (0x44) 7-5 unused r - unused 4-0 agcstep1 rw 0x0e defines the 1st agc threshold regagcthresh2 (0x45) 7-4 agcstep2 rw 0x05 defines the 2nd agc threshold: 3-0 agcstep3 rw 0x0b defines the 3rd agc threshold: regagcthresh3 (0x46) 7-4 agcstep4 rw 0x0d defines the 4th agc threshold: 3-0 agcstep5 rw 0x0b defines the 5th agc threshold: regpllhop (0x4b) 7 fasthopon rw 0x00 bypasses the main state machine for a quick frequency hop. writing regfrflsb will trigger the frequency change. 0 ? frf is validated when fstx or fsrx is requested 1 ? frf is validated triggered when regfrflsb is written 6-0 reserved rw 0x2e reserved regtcxo (0x58) 7-5 reserved rw 0x00 reserved. retain default value 4 tcxoinputon rw 0x00 controls the crystal oscillator 0 ? crystal oscillator with external crystal 1 ? external clipped sine tcxo ac-connected to xta pin 3-0 reserved rw 0x09 reserved. retain default value. regpadac (0x5a) 7-3 reserved rw 0x10 reserved. retain default value 2-0 padac rw 0x04 enables the +20dbm option on pa_boost pin 0x04 ? default value 0x07 ? +20dbm on pa_boost when outputpower= 1111 name (address) bits variable name mode default value description
www.semtech.com page 84 sx1235 wireless & sensing datasheet rev 1 - december 2012 regpll (0x5c) 7-6 pllbandwidth rw 0x03 controls the pll bandwidth: 00 ? 75 khz 10 ? 225 khz 01 ? 150 khz 11 ? 300 khz 5-0 reserved rw 0x10 reserved. retain default value regplllowpn (0x5e) 7-6 pllbandwidth rw 0x03 controls the low phase noise pll bandwidth: 00 ? 75 khz 10 ? 225 khz 01 ? 150 khz 11 ? 300 khz 5-0 reserved rw 0x10 reserved. retain default value regpllgopt 7-0 loopgain rw 0x32 controls the pll loop gain and other settings 0x37 ? category 1 phase noise optimization 0x32 ? all other applications regformertemp (0x6c) 7-0 formertemp rw - temperature saved during the latest iq (rssi and image) calibrated. same format as tempvalue in regtemp . regbitratefrac (0x70) 7-4 unused r 0x00 unused 3-0 bitratefrac rw 0x00 fractional part of the bit rate divider (only valid for fsk) if bitratefrac > 0 then: name (address) bits variable name mode default value description bitrate fxosc bitrate 15 0 (,) bitratefrac 16 ------------------------------- + ------------------------------------------------------------------------- =
www.semtech.com page 85 sx1235 wireless & sensing datasheet rev 1 - december 2012 7. application information 7.1. crystal resonator specification table 34 shows the crystal resonator sp ecification for the crystal reference oscillator circuit of the sx1235. this specification covers the full range of operation of the sx1235 and is employed in the reference design. table 34 crystal specification notes - the initial frequency tolerance, temper ature stability and ageing performance should be chosen in accordance with the target operating temperature range and the receiver bandwidth selected. - the loading capacitance should be applied externally, and adapted to the actual cload specification of the xtal. 7.2. reset of the chip a power-on reset of the sx1235 is trig gered at power up. additionally, a manual reset can be issued by controlling pin 6. 7.2.1. por if the application requires the disconnectio n of vdd from the sx1235, despite of th e extremely low sleep mode current, the user should wait for 10 ms from of the end of the por cycle before commencing communications over the spi bus. pin 6 (reset) should be left floating during the por sequence. figure 41. por timing diagram please note that any clkout activity can also be used to detect that the chip is ready. symbol description conditions min typ max unit fxosc xtal frequency - 32 - mhz rs xtal serial resistance - 30 140 ohms c0 xtal shunt capacitance - 2.8 7 pf cfoot external foot capacitance on each pin xta and xtb 8 15 22 pf cload crystal load capacitance 6 - 12 pf wait for 10 ms vdd pin 6 (output) chip is ready from this point on undefined
www.semtech.com page 86 sx1235 wireless & sensing datasheet rev 1 - december 2012 7.2.2. manual reset a manual reset of the sx1235 is possible even for applicat ions in which vdd cannot be physically disconnected. pin 6 should be pulled high for a hundred microseconds, and then releas ed. the user should then wait for 5 ms before using the chip. figure 42. manual reset timing diagram note whilst pin 6 is driven high, an ov er current consumption of up to ten milliamps can be seen on vdd. 7.3. reference designs please contact your semtech representative for evaluation tool s, reference designs and design assistance. note that all schematics shown in this section are fu ll schematics, listing all re quired components, including decoupling capacitors. figure 43. reference design - single rf input/output, high efficiency pa vdd > 100 us chip is ready from this point on pin 6 ( in p ut ) high-z high-z ??1?? wait for 5 ms
www.semtech.com page 87 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 44. reference design - with antenna switch up to +20dbm figure 45. reference design - with antenna switch and high efficiency pa
www.semtech.com page 88 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 46. reference design - single rf input/output, high stability pa note the implementation of figure 46 is limited to +14dbm operation for detailed bills of materials, please c onsult the reference design se ction on the sx1235 web page , or contact your local semtech representative.
www.semtech.com page 89 sx1235 wireless & sensing datasheet rev 1 - december 2012 7.4. top sequencer: listen mode examples in this scenario, the circuit spe nds most of the time in idle m ode, during which only the rc o scillator is on. periodically the receiver wakes up and looks for incoming signal. if a wanted signal is detected, the receiver is kept on and data are analyzed. otherwise, if there was no wanted signal for a defined period of time, the receiver is switched off until the next receive period. during listen mode, the radio stays most of the time in a low power mode, resulting in very low average power consumption. the general timing diagram of this scenario is given in figure 47. figure 47. listen mode: principle an interrupt request is generated on a packet rec eption. the user can then take appropriate action. depending on the application and environment, ther e are several ways to implement listen mode: ? wake on a preambledetect interrupt ? wake on a syncaddress interrupt ? wake on a payloadready interrupt 7.4.1. wake on preamble interrupt in one possible scenario, the sequencer polls for a preamble detection. if a preamble signa l is detected, the sequencer is switched off and the circuit stays in receive mode until the user switches modes. otherwise, th e receiver is switched off until the next rx period. 7.4.1.1. timing diagram when no signal is received, the circuit wakes every timer1 + timer2 and switches to receive mode for a time defined by timer2, as shown on the following diagram. if no preamble is detected, it then switches back to idle mode, i.e. sleep mode with rc oscillator on. figure 48. listen mode with no preamble received listen mode : principle receive receive idle ( sleep + rc ) idle no received signal receive receive idle ( sleep + rc ) idle timer2 timer1 timer2 timer1 timer1
www.semtech.com page 90 sx1235 wireless & sensing datasheet rev 1 - december 2012 if a preamble signal is detected, the sequencer is switched off. the preambledetect signal can be mapped to dio4, in order to request the user's attention. t he user can then take appropriate action. figure 49. listen mode with preamble received 7.4.1.2. sequencer configuration the following graph shows listen mode - wake on preambledetect state machine: figure 50. wake on preambledetect state machine this example configuration is achieved as follows: table 35 listen mode with preambledetect condition settings variable effect idlemode 1 : sleep mode fromstart 00 : to lowpowerselection lowpowerselection 1 : to idle state fromidle 1 : to receive state on t1 interrupt fromreceive 110 : to sequencer off on preambledetect interrupt timer2 received signal preamble ( as long as t1 + 2 * t2 ) sync word payload crc receive idle ( sleep + rc ) timer1 preamble detect timer2 state machine lowpower selection idle receive lowpowerselection = 1 on t2 on t1 fromidle = 1 on preambledetect fromreceive = 110 sequencer off idlemode = 1 : sleep start sequencer off & initial mode = sleep or standby start bit set fromstart = 00
www.semtech.com page 91 sx1235 wireless & sensing datasheet rev 1 - december 2012 t timer2 defines the maximum duration the chip stays in receive mode as long as no preamble is detected. in order to optimize power consumption, timer2 must be set just long enough for preamble detection. t timer1 + t timer2 defines the cycling period, i.e. time between two pr eamble polling starts. in or der to optimize average power consumption, timer1 should be re latively long. however, increasing timer1 also extends packet reception duration. in order to insure packet detection and optimize the receiv er's power consumption, the received packet preamble should be as long as t timer1 + 2 x t timer2 . an example of dio configuration for this mode is described in the following table: table 36 listen mode with preambledetect condition recommended dio mapping 7.4.2. wake on syncaddress interrupt in another possible scenario, the sequencer polls for a preamble detection and then for a valid syncaddress interrupt. if events occur, the sequencer is switched off and the circui t stays in receive mode unt il the user switches modes. otherwise, the receiver is switch ed off until the next rx period. 7.4.2.1. timing diagram most of the sequencer running time is spent while no want ed signal is received. as shown by the timing diagram in figure 51, the circuit wakes periodically for a short time, defined by rxtimeout. the circuit is in a low power mode for the rest of timer1 + timer2 (i.e. timer1 + timer2 - trxtimeout) figure 51. listen mode with no syncaddress detected if a preamble is detected before rxtimeout timer ends, the circuit stays in receive mode and waits for a valid syncaddress detection. if none is de tected by the end of time r2, receive mode is deacti vated and the polling cycle resumes, without any user intervention. dio value description 001crcok 1 00 fifolevel 300fifoempty 4 11 preambledetect ? note: mappreambledetect bit should be set. no wanted signal receive receive idle ( sleep + rc ) idle idle timer2 timer1 timer2 timer1 timer1 rxtimeout rxtimeout
www.semtech.com page 92 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 52. listen mode with pr eamble received and no syncaddress but if a valid sync word is detected, a syncaddress interrupt is fired, the sequencer is switched off and the circuit stays in receive mode as long as the user doesn't switch modes. figure 53. listen mode with preamble received & valid syncaddress 7.4.2.2. sequencer configuration the following graph shows listen mode - wake on syncaddress state machine: unwanted signal preamble ( preamble + sync = t2 ) wrong word payload crc preamble detect receive receive idle idle idle timer2 timer1 timer2 timer1 timer1 rxtimeout rxtimeout wanted signal preamble ( preamble + sync = t2 ) sync word payload crc preamble detect receive idle timer2 timer1 sync address fifo level rxtimeout
www.semtech.com page 93 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 54. wake on syncaddress state machine this example configuration is achieved as follows: table 37 listen mode with syncaddress condition settings t timeoutrxpreamble should be set to just long enough to catch a preamble (depends on preambledetectsize and bitrate ). t timer1 should be set to 64 s (shortest possible duration). t timer2 is set so that t timer1 + t timer2 defines the time between two start of reception. in order to insure packet detection and optimize the receiver power consumption, the received packet preamble should be defined so that t preamble = t timer2 - t syncaddress , with t syncaddress = ( syncsize + 1 ) *8/ bitrate . an example of dio configuration for this mode is described in the following table: table 38 listen mode with preambledetect condition recommended dio mapping variable effect idlemode 1 : sleep mode fromstart 00 : to lowpowerselection lowpowerselection 1 : to idle state fromidle 1 : to receive state on t1 interrupt fromreceive 101 : to sequencer off on syncaddress interrupt fromrxtimeout 10 : to lowpowerselection dio value description 001crcok 1 00 fifolevel 2 11 syncaddress 300fifoempty 4 11 preambledetect ? note: mappreambledetect bit should be set. state machine lowpower selection idle receive rxtimeout lowpowerselection = 1 fromrxtimeout = 10 on rxtimeout on t2 on t1 fromidle = 1 on syncadress fromreceive = 101 sequencer off idlemode = 1 : sleep start fromstart = 00 sequencer off & initial mode = sleep or standby start bit set
www.semtech.com page 94 sx1235 wireless & sensing datasheet rev 1 - december 2012 7.5. top sequencer: beacon mode in this mode, a repetitive message is transmitted periodically. if the payload being sent is always identical, and payloadlength is smaller than the fifo size, the use of the beaconon bit in regpacketconfig2 together with the sequencer permit to achieve periodic beacon without any user intervention. 7.5.1. timing diagram in this mode, the radio is switched to transmit mode every t timer1 + t timer2 and back to idle mode after packetsent , as shown in the diagram below. the sequencer insures minima l time is spent in transmit mode, and therefore power consumption is optimized. figure 55. beacon mode timing diagram 7.5.2. sequencer configuration the beacon mode state machine is presented in the following gr aph. it is noticeable that the sequencer enters an infinite loop and can only be stopped by setting sequencerstop bit in regseqconfig1 . figure 56. beacon mode state machine beacon mode transmit transmit idle ( sleep + rc ) idle idle timer2 timer1 timer1 timer1 timer2 packet sent packet sent state machine transmit on t1 fromidle = 0 on packetsent fromtransmit = 0 lowpower selection idle lowpowerselection = 1 idlemode = 1 : sleep start fromstart = 00 sequencer off & initial mode = sleep or standby start bit set
www.semtech.com page 95 sx1235 wireless & sensing datasheet rev 1 - december 2012 this example is achieved by programming the sequencer as follows: table 39 beacon mode settings t timer1 + t timer2 define the time between the start of two transmissions. variable effect idlemode 1 : sleep mode fromstart 00 : to lowpowerselection lowpowerselection 1 : to idle state fromidle 0 : to transmit state on t1 interrupt fromtransmit 0 : to lowpowerselection on packetsent interrupt
www.semtech.com page 96 sx1235 wireless & sensing datasheet rev 1 - december 2012 7.6. example crc calculation the following routine(s) december be implemen ted to mimic the crc calculation of the sx1235: figure 57. example crc code
www.semtech.com page 97 sx1235 wireless & sensing datasheet rev 1 - december 2012 7.7. example temperature reading the following routine(s) december be implemented to read the temperature and calibrate the sensor: figure 58. example temperature reading
www.semtech.com page 98 sx1235 wireless & sensing datasheet rev 1 - december 2012 7.8. etsi category 1 quick start to correctly configure the sx1235 for etsi category 1 operation, it is necessary to enable some specific functionality within the receiver. the following description highlights the settings required to enable and realize the category 1 performances of the sx1235. 7.8.1. pll settings the sx1235 features a single pll for use in reception. co rrectly configured, the pll becomes the component of the receiver system that has the gr eatest contribution to the adjacent channel perf ormances of the receiver. by minimizing the phase noise, the rejection afforded in the adjacent channels is increased. the default pll bandwidth setting provides the lowest phase noise in the 12.5 khz and 25 khz frequency offsets. however, by modification of the loop gain setting it is possible to further improve the phase noise in this frequency range. the regpllgopt (address 0x5f) should be written to value 0x37. with this setting the resultant phase noise is shown in the figure below. figure 59. sx1235 optimised phase noise at 12.5 khz and 25 khz 7.8.2. channel filter settings the dominance of the phase noise on the adjacent channe l rejection performance of the sx1235 assumes that the receiver channel filtration is correctly configured. two receiver channel filter bandwidths are accessible during the reception of data: the first, the afc bandwidth is the bandwidth used during reception of preamble and alignment of the receiver. the second, the communication (rx) bandwidth is that used for the ensuing communication phase. these must be suitably wide that the total crystal error and modulation bandwidth of the signal can be accommodated by the receiver during the afc phase. the narrower communication bandwidth mu st then be at least as wi de as the received signal?s modulation bandwidth. to ensure the highest link quality the -20 db bandwidth of the receiver filter is declared. the figure below illustrates the difference between these three filter settings and the conventions used in the use of either double or single side band used.
www.semtech.com page 99 sx1235 wireless & sensing datasheet rev 1 - december 2012 figure 60. sx1235 filter definitions and conventions to aid with the selection of the appropriate bandwidth sett ings the programmable filter steps relevant to narrow band category 1 applications are shown below table 40 category 1 narrowband filter settings for sx1235 rxbwmant (binary/value) rxbwexp (decimal) bw (khz) afc or rx declared bw -20 db (khz) intermediate frequency (khz) 10b / 24 7 2.6 6.2 166.66 01b / 20 7 3.1 7.4 200 00b / 16 7 3.9 9.4 250 10b / 24 6 5.2 12.5 166.66 01b / 20 6 6.3 15.1 200 00b / 16 6 7.8 18.7 250 10b / 24 5 10.4 24.9 166.66 01b / 20 5 12.5 - 200 00b / 16 5 15.6 - 250 10b / 24 4 20.8 - 166.66 01b / 20 4 25.0 - 200
www.semtech.com page 100 sx1235 wireless & sensing datasheet rev 1 - december 2012 7.8.3. image frequency also shown in the preceding table is the intermediate freq uency (if) used depending upon which receiver bandwidth is used. because the sx1235 features a low if based upon a local oscilla tor lower in frequency than the rf centre frequency the resulting image frequency, at which there is a spurious response, is as shown below: figure 61. sx1235 spurious image response frequency this spurious image response frequency is hence located at twice the intermediate frequency below the wanted signal frequency. table 41 sx1235 image and intermediate frequency values. the sx1235 features an image rejection filt er which, when calibrated, is capabl e of providing over 45 db of image rejection. to ensure the highest quality calibration, and so the best image rejection, calibration procedure outlined below should be performed following reset of the circuit or after a significant temperature change (see tempchange flag). step 1. register address 0x0e should be written to 0x07 to increase the rssi smoothing value to 256. step 2. trigger the image calibration by writing to register address 0x3b with the contents 0x22. step 3. wait 8 ms step 4. register address 0x0e should be written to 0x02 to return the rssi smoothing value to default. 7.8.4. tcxo settings the use of narrow band channels in the category 1 regulation s means that a tcxo is typically required. use of the tcxo is enabled by setting bit tcxoinputon of register regtcxo . for connection of the tcxo see figure 9. rxbwmant (binary) if (khz) image frequency 00b 250 f rf - 500 khz 01b 200 f rf - 400 khz 10b 166.6 f rf - 333 khz
www.semtech.com page 101 sx1235 wireless & sensing datasheet rev 1 - december 2012 8. packaging information 8.1. package outline drawing the sx1235 is available in a 24-lead qfn package as shown in figure 62. figure 62. package outline drawing 8.2. recommended land pattern figure 63. recommended land pattern millimeters 0.65 bsc 0.00 a1 e1 aaa bbb n e l a2 d1 d e b 0.35 4.90 4.90 3.20 - 0.25 dim a dimensions 0.80 min - 0.05 5.10 5.10 3.30 0.45 0.35 0.40 0.10 0.08 24 5.00 (0.20) 3.25 5.00 0.30 - 1.00 max - nom b aaa c 3.20 3.25 3.30 d e a a2 a1 e/2 e bxn lxn e/2 d/2 d1 e1 c seating plane 1 2 n bbb c a b coplanarity applies to the exposed pad as well as the terminals. controlling dimensions are in millimeters (angles in degrees). notes: 2. 1. a pin 1 indicator (laser mark) k h g z (c) y p x this land pattern is for reference purposes only. consult your manufacturing group to ensure your notes: 2. dim x y h k p c g millimeters (4.90) 0.35 0.80 3.30 0.65 3.30 4.10 dimensions company's manufacturing guidelines are met. 5.70 z failure to do so may compromise the thermal and/or functional performance of the device. shall be connected to a system ground plane. thermal vias in the land pattern of the exposed pad 3. 4. square package-dimensions apply in both x and y directions. controlling dimensions are in millimeters (angles in degrees). 1.
www.semtech.com page 102 sx1235 wireless & sensing datasheet rev 1 - december 2012 8.3. thermal impedance the thermal impedance of this package is: theta ja = 23.8 c/w typ. , calculated from a package in still air, on a 4-layer fr4 pcb, as per the jedec standard. 8.4. tape & reel specification figure 64. tape & reel specification note single sprocket holes
www.semtech.com page 103 sx1235 wireless & sensing datasheet rev 1 - december 2012 9. revision history table 42 revision history revision date comment 1 december 2012 first release
www.semtech.com page 104 semtech corporation wireless & sensing products division 200 flynn road, ca marillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 e-mail: sales@semtech.com support_rf@semtech.com internet: http://www.semtech.com contact information sx1235 wireless & sensing datasheet rev 1 - december 2012 ? semtech 2012 a ll rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. th e information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customer?s own risk. should a customer purchase or use semtech product s for any such unauthorized application, the customer shall indemnify and hold semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.

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